Fluke 9132A, Руководство по обслуживанию

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9132A Service
24-, 28-, or 32-pin ROM Modules. The adapters also take the power pin
from the particular ROM Module
(i.e., 24-, 28-, or 32-pin) and
run it to the
appropriate line
on
J2 for
the power
fail
detector
line.
Self Test Assembly
2-13.
The Self Test Assembly schematic diagram
is
shown
in Figure 5-2.
The latched address lines from the Pod processor pass through protection
hybrids
(Al,
A2, and A3) and drive various pins
on
either the ROM Module
assemblies
on J1
(a
32-pin
ZIF socket), J2
(a
40-pin ZIF socket), or J4 (the
Sync Module Connector). The
lines that are output from the Sync Module or
the ROM Modules
are
received at these sockets, pass through
the
hybrids,
and
are
passed to readable data
lines.
RAM
Module or Emulation
RAM
2-14.
The RAM Module schematic diagram
is shown in
Figure 5-4.
The RAM Module contains two separate RAM chips
(US and U6). US
is
emulation RAM
A,
and U6
is emulation RAM
B.
Each bank of
emulation
RAM
has a
separate set
of address
lines.
This allows one bank to
communicate with the Pod processor while
the other bank is used
by
the
ROM Modules.
The data lines from the banks of RAM
go
to
one
of
a
pair of data buffers
(U3
or U4), so that whichever bank is communicating with the Pod processor
sends data through the selected buffer
back to the Pod data lines. The other
bank passes data through a pair of muxes
(U7 and US),
through a back-
terminating resistor package
(Z1),
and
to the
ROM Module data
bus.
This
data bus
goes
through the buffers
on the
ROM Module
and out to the UUT
ROM data
lines.
Personality Module
2-15.
The Personality Module contains
no
user-serviceable parts.
The Personality Module is processor dependent,
but always has one PROM
and one PAL. ‘Some Personality Modules, such as the one for the 80286
processor, have extra inverters for some
of
the input lines (one inverter is
used for the clock
line, and
others were used
on
other inputs to match
delays, thereby avoiding timing skew problems).
Jumpers
W1 and W2
allow for swapping between
a
27C256 or
a
27C512 ROM (normally W2
is
wired to the board for a 27C256
ROM).
Jumpers W3 and
W4 determine the polarity for driving channel
3 (CH3)
either high or low upon the timed receipt of
the
overdrive channel
3
(OVDRVCH?3) request.
'W3 is installed
to
overdrive low. The polarity of
the
OVDRV-OUT signal
is
processor dependent.
The inputs to
the PAL include the
seven
input channels from the
Sync
Module, request reset (REQRESET), overdrive channel 3 (to
overdrive
either high or low), the sync control
lines (PSYNCCTL1,
2,
and
3),
and
ROMISEL (which is the active bus cycle clock from the ROM Modules).
The outputs from the PAL
are
the
sync
clock (which depends
on
the
sync
2-15