Fluke 9132A, Руководство по обслуживанию

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9132A Service
from the Personality Module
is
used
as
the counter clock. When
the counter
reaches its maximum value, SC11 is set. On the first rising edge of
SYNCCLK- after
SC11 is set, the
SYNC signal
on
the PAL (U32
pin 15)
goes true.
On the
second rising edge of SYNCCLK-, the SYNC signal goes
inactive.
In the second method, the RESET-LAT signal from
the Personality Module
arms the PAL.
For
this
method
to
work, ARMSEL must be low.
Once
the
PAL
is armed, the same events occur
as
occurred
using
the ARM
signal.
The
ARM-
signal
to the generic PAL
(U32)
is
created
in
the circuit made
up
of U26A
and U9D.
Clock latch (CLKLATCH)
is
ANDed with data sync
(DATASYNC). If data
sync
is already valid
when
clock latch goes
high,
ARM- is issued immediately. If data
sync is
not valid, ARM- is
delayed
until data
sync goes true. This method eliminates race conditions between
the ROM1 chip select and
the data
sync
clock, and
guarantees that both
signals are present before the sync counter clock begins counting.
When ARMSEL
on
the PAL
is
selected and BCCLK-
(pin 10) goes true,
ARAM-CLK and ARAM-CLK-
toggle.
When
AC-11
goes high, ARAM-
CLK and ARAM-CLK- toggle back to their original values.
SSO
and
SS1 on the PAL
are the sync state signals.
Table 2-1 shows the
type
of
sync state,
the condition of
SSO and SS1, and a
definition of the
signal
state.
The FRC-SYNC line on the
PAL
is
used
for self
test.
Table 2-1.
State
Definitions for the Sync State Machine
SYNC STATE $51
|
SS0
|
DEFINITION
OFF 0 0
Disabled, ARMEN IS
FALSE.
IDL 0
1
Enabled, waiting
for
first
clocked armed
condition.
WAIT
1 1
Enabled and armed, waiting for SC11.
DONE
1
0 Finished, SC11
seen while armed.
Main Board
ROM Module
Connections
2-9.
The Main Board ROM Module connections
are shown on page
7
of the Main
Board schematic (Figure
5-1).
J1 connects
to
the Pod cable from the 9100
Series
Mainframe. J4 through
J11
connect in pairs
to
ROM Modules
1
through 4.
The test connector
(J16)
accesses
the
raw Pod processor address and
data
bus.
This connector
is
the same
as
found
on
the Mainframe main board
(i.e.,
for the test access
card).
Sync Module
2-10.
2-12
The
Sync
Module schematic diagram
is
found
in Figure 5-3.
The
Sync
Module
is basically a buffer
to
monitor several of
the
lines
to the
UUT microprocessor (eight data
lines,
and eight status
and
control lines)
and to drive the cable. The inputs from the UUT come through J2, pass
through a protection hybrid (Al),
a
buffer
(U2,
U3), a resistor pack (Z1, 72)