Fluke 9132A, Руководство по обслуживанию

Страница: 19 / 92

9132A Service
The outputs of the
U27 flip-flops are ANDed for ROM bank select
(ROMBANKSEL) and
bank available (BANKAAVAIL, BANKAAVAIL-,
BANKBAVAIL, and BANKBAVAIL-). These five
lines select which bank
is available to the Pod processor, which bank is available to the ROM
Module, and which bank has readable
bits.
RUNUUT
1,
2, 3,
and 4 are separate outputs to ROM Modules 1,
2, 3,
and
4.
These lines control chip enable
(CE)
and output enable
(OE)
for the UUT
boot ROMs located in the ZIF socket of the ROM Modules. U21A
is the
RUNUUT
flip-flop. This flip-flop is set by
RUNUUTREQ to the data input
pin
(pin 2)
and
the
sync counter output (SC11) to
the
clock input
pin
(pin
3).
The flip-flop is
swapped
when
the
Pod is in
RUNUUT mode and
the
SC11
line goes
true. (In
some hardware modes,
SC11 can be
forced
by
the
processor
to
not be a true timer signal) The AND/OR gates U4C
and
U37D
allow
a
read from the boot ROM plugged into the
UUT ROM Module to
occur, dynamically switching the ROM Module
in and
out of RUNUUT mode
for
one bus cycle. This switching occurs only if sync
mode is set
to
data
sync
(because this is
the only time that data is valid). Once the SYNC line
goes active, one
bus cycle is clocked to Pod
sync
if the Pod is in
data sync
mode with the ROM-TST-EN bit
set.
When the clocked bus cycle occurs,
the ROM Modules switch the emulation RAMs out and the
ROM in, which
lets the UUT
processor
read
the data that
is
located in the UUT ROM.
Main Board Emulation
RAM
Connectors and Self Test 2-5.
2-6
The Main Board Emulation RAM connectors and self test circuitry are
shown on page 3 of the Main Board schematic (Figure
5-1).
J12,
113,
J14, and J15 are the
sockets for
the
emulation RAM Modules. For
each ROM Module connected
to
the Pod, a corresponding RAM Module is
plugged into these sockets. Each RAM Module has two
banks.
The lines
into these connectors are bank enable, and address and data lines in
and
out. The emulation RAM Modules are explained further on in this section.
The self test board connector is attached
by
a ribbon cable to the self test
board. Self
test is
accessed
when A23 is high.
During self test read or
write,
all
other address lines go
to
the address latches U104, U23, and U76.
When self test latch enable (ST-LE)
is true,
these latches are transparent,
allowing the
addresses
to go straight to the different self test pins. At the
end of self test, the addresses that
are
latched remain stable and do not
change until the next self test
access.
The data path from the self test board connector goes to U100 and U103,
which
are
noninverting data buffers. Whatever
is
on
the pins
is gated to the
Pod data bus
when
self test output enable
(ST-OE)
is true
(i.e., during any
self
test
read).
One of the pins
on the
ROM Module
(pin 24, 28,
or 32) must have +5V
power
when
plugged into the self
test
socket. Three relays
(K1,
K2,
and
K3)
switch power to the appropriate
pin,
depending on the
type
of ROM
Module. The self test control lines (SLFTST-CNTL-28, SLFTST-CNTL-
30, and SLFTST-CNTL-32) choose which
of
the
relays
is
activated.