Fluke 9132A, Руководство по обслуживанию

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9132A Service
(OVDRV-RESET)
is
gated
through USB and
USC along with reset polarity
(RESETPOL) to determine
when
the overdrive is requested
and also
determine the polarity of
the reset signal.
The processor-specific Personality Module plugs into connector
J2.
The
Personality Module contains two devices, a ROM
and a PAL. The ROM on
the Personality Module is connected to address
lines
1
through 16
and data
lines
0 through 7. When the personality ROM
is
selected (using
PMROMSEL), the data in the ROM is placed
on
the data
bus.
All ROM
code
is uploaded
at
Pod power-on to the main Pod RAM where it
is
executed. (The code
is not executed directly from the ROM Module since
the ROM Module is only
byte
wide, and
Pod processor instruction data
must be
word wide to use.)
The other device in
the
Personality Module
is the Personality Module
PAL.
This PAL uses the clock
and
seven channel inputs from the
Sync Module.
Other lines going to the PAL are reset request (REQRESET), the
sync
control lines (PSYNCCTLx),
and overdrive channel
3 (OVDRV3).
The
PAL decodes these
lines and
outputs four signals.
One signal
is
called data
sync
(DATASYNC),
a
timing signal that shows data bus accesses
at
the
UUT. Another signal
is
called sync clock (SYNCCLK-), a line that can
either act the same
as
the data
sync
or can be set to another time to
show
the timing of the address pulses. RESET-LAT latches true when a UUT
reset
is
detected,
and is
cleared by REQRESET
in
clear mode or by
the
PSYNCCTLx control
lines. RESET-LAT
is
used
as an
initialization or arm
for
the generic PAL in
some modes.
The last signal is bus cycle clock
(BCYCLECLK-). This
signal
can be set
the same
as
data
sync,
or it can be
set the same
as
the ROM Module
1
select
(an
input to the
PAL
in
the
Personality Module).
The last line going to the Personality Module is called personality present
bar (PM-PRESENT-). This signal
is grounded whenever the Personality
Module
is
installed. PM-PRESENT- is monitored
at
input port U12 pin 6.
U20 and U30A make
up
a circuit that generates the
UUT clock fail (CLK-
FAIL) signal. U20
is a timer that continuously resets itself to zero each
time
an
active clock edge is received from the UUT. If the circuit does not
receive
a
clock edge within five E clocks, U20 generates a clock fail (CLK-
FAIL) signal.
U4D monitors overdrive channel
3 (OVDRVCH3) and state machine
zero
(880). U4D
twrns
off overdrive 3 (OVDRV3) immediately after the SYNC
pulse is
generated. This reduces the amount of time channel
3
is overdriven,
since the Personality Module
no
longer needs OVDRV3 once the SYNC
pulse
is
generated.
The generic PAL (U32) controls
all the sync counter timing and the address
RAM counter timing. There are two methods of arming the
PAL.
In
the first method, ARM is used
as the arm for
the PAL. When the arm
signal is input to the PAL and arm enable (ARMEN) and arm select
(ARMSEL)
are
true, the PAL outputs the sync count enable (SCNT-EN-).
The SCNT-EN- signal enables
a set
of counters
(U41,
U42, and U2).
These counters were previously
set
to a specific value by the Pod
processor.
When the SCNT-EN-
signal is
enabled, the SYNCCLK- signal
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