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FIC MB05W Service Manual
FIC MB05 Service Manual
1-81
System Interrupts
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. Supports Intel 8259 and processor system bus interrupt delivery mechanism
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. Supports interrupts signaled as upstream memory writes from PCI and Hub interface
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. MSI sent to the CPU through the system bus
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. IOxAPIC in ICH4-M provides redirection for upstream interrupts to the system bus
Video Stream Decoder
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. Improved hardware motion compensation for MPEG2
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. All format decoder (18 ATSC formats) supported
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. Dynamic Bob and Weave support for video streams
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. Software DVD at 60 Fields/second and 30 frames/second full screen
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. Support for standard definition DVD (i.e. NTSC pixel resolution of 720x480, etc.) quality
encoding at low CPU utilization
Video Overlay
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. Single high quality scalable overlay and second Sprite to support second overlay
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. Multiple overlay functionality provided via arithmetic stretch BLT(Block Transfer)
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. 5-tap horizontal, 3-tap vertical filtered scaling
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. Multiple overlay formats
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. Direct YUV from overlay to TV-out
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. Independent gamma correction
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. Independent brightness / contrast/ saturation
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. Independent tint/hue support
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. Destination colorkeying
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. Source chromakeying
Multiple hardware color cursor support (32-bit with alpha and legacy 2-bpp
mode)
Accompanying I2C and DDC channels provided through multiplexed interface
Display
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. Analog display support
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350-MHz integrated 24-bit RAMDAC that can drive a standard progressive scan
analog monitor with pixel resolution up to 1600x1200 at 85 Hz and up to 2048x1536
at 75 Hz
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. Dual independent pipe support
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Concurrent: Different images and native display timings on each display device
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Simultaneous: Same images and native display timings on each display device
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. DVO (DVOB and DVOC) support
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Digital video out ports DVOB and DVOC with 165-MHz dot clock on each 12-bit
interface; two 12-bit channels can be combined to form one dual channel 24-bit
interface with an effective dot clock of 330-MHz
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The combined DVO B/C ports as well as individual DVO B/C ports can drive a
variety of DVO devices (TV-Out Encoders, TMDS and LVDS transmitters, etc.) with
pixel resolution up to 1600x1200 at 85 Hz and up to 2048x1536 at 72 Hz.
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Compliant with DVI Specification 1.0
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R
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. Dedicated LFP (local flat panel) LVDS interface
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Single- or dual-channel LVDS panel support up to UXGA panel resolution with
frequency range from 25 MHz to 112 MHz (single channel/dual channel)
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Supports data format of 18 bpp
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SSC support of 0.5%, 1.0%, and 2.5% center and down spread with external SSC
clock
LCD panel power sequencing compliant with SPWG timing specification
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