FAURE-HERMAN
COMPONENT MAINTENANCE MANUAL
744-082 / 744-082-3
28-49-91
PAGE 10
MAR 31/07
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B000 : Validation of the helicopter type and unit of measure selector switches (MN206),
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C000 : Input validation (face panel control pushbuttons (IC13),
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D000 : RAM validation (IC5),
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F000 : EPROM read enable (MN203).
A clock circuit required for microprocessor operation is provided using 4 MHz quartz (Ql)
and capacitors C1 and C2.
The data bus operation (read or write, is determined by a direction indicator (IC2) controlled
by the microprocessor.
(3)
Watchdog (See sheet 2)
The watchdog comprises a monitoring circuit chiefly consisting of double monostable IC1,
inverter circuits IC15, and NAND gates IC9 with a trigger effect. The microprocessor and
the RAM memory are reset by this circuit in the following instances :
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28 V source power drops to a low level and induces an NMI interrupt signal. When fed
with this signal, the microprocessor stores its data in the RAM memory and performs a
delayed reset via circuits IC9 (3), IC15 (3) and R6/C22.
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Switching on + 28 V voltage again. Upon voltage restoration, a reset is performed by
circuits IC9 (3), IC1 (3) for a time constant determined by circuit R6/C22. At the same
time, the first monostable of circuit IC1 trips in via circuits IC9 (4) and IC15 (4), in
accordance with the microprocessor clock signal. The second monostable is then
triggered. When the output voltage increases to + 5 V, the second monostable cancels the
"RESET" signal through circuits IC9 (3) et IC15 (3) in accordance with the d 5 V
voltage of circuit R6/C22.
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Absence of correct operation signal. This signal is delivered by monitoring circuit IC11
which regularly resets the watchdog through circuit IC2 if the program proceeds as
required. When this signal is absent, the watchdog trips in and sends a "RESET" pulse to
the microprocessor and the RAM memory.
The document reference is online, please check the correspondence between the online documentation and the printed version.