EVGA X299 DARK, Руководство пользователя

Страница: 27 / 152

EVGA X299 DARK (151-SX-E299)
- 27 -
PCIe Slot Breakdown (Skylake-X)
PCIe Lane Distribution (Core ™ i9-79xx, 44 Lane
Processors)

PE1 – x16 (Gen3, x16 lanes from CPU, x8 shared with PE2)

PE2 – x16 (Gen3, x8 lanes from CPU, shares 8 of PE1’s 16 lanes)

PE3 – x16 (Gen3, x8 lanes from CPU, shares 8 of PE4’s 16 lanes)

PE4 – x16 (Gen3, x16 lanes from CPU, x8 shared with PE3)

PE5 – x4 (Gen3, x4 lanes from PCH)

PE6 – x16 (Gen3, x8 lanes from CPU or x4 from PCH based on
configuration)
o
When populated by a video card x8 Gen3 lanes are allocated from the
CPU
o
When populated by a card using x4 or x1 lanes, and M.2 80mm slot is
populated PE6 receives x4 lanes from the PCH
PCIe Lane Distribution (Core
™
i7-78xx, 28 Lane
Processors)

PE1 – x16 (Gen3, x16 lanes from CPU, x8 shared with PE2)

PE2 – x16 (Gen3, x8 lanes from CPU, shares 8 of PE1’s 16 lanes)

PE3 – x16 (Not functional on 28 lane processors)

PE4 – x16 (Gen3, x8 lanes from CPU)

PE5 – x4 (Gen3, x4 lanes from PCH)

PE6 – x16 (Gen3, x4 lanes from PCH)
o
Must be enabled in BIOS, which disables M.2 80mm