EVGA 37062314, Руководство пользователя

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EVGA Z390 DARK (131-CS-E399)
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PCIe Slot Breakdown
PCIe Lane Distribution (All Socket 1151
processors are 16 lanes.)

PE1 – x16 (Gen3, x16 lanes from CPU, x8 shared with PE2)

PE2 – x8 (Gen3, x8 lanes from CPU, x4 shared with PE4)

PE3 – x4 (Gen3, x4 lanes from PCH)

PE4 – x4 (Gen3, x4 lanes from CPU, shares 4 of PE2’s 8 lanes)
M.2 / U.2 Slot Breakdown
M.2 Lane Distribution

M.2 Key-M (110mm, Top, PM1) – x4 from Z390 PCH
o
M.2 Enable/Disable is set within the BIOS
o This M.2 Key-M slot shares lanes with the U.2 port. Installing an M.2
device will disable U.2 port PU1.

M.2 Key-M (110mm, Bottom, PM2) – x4 from Z390 PCH
o
M.2 Enable/Disable is set within the BIOS
o
This M.2 Key-M slot shares lanes with PE3. Installing an M.2 device will
disable PCIe slot PE3.

M.2 Key-E (32mm) – x1 from Z390 PCH
o
M.2 Enable/Disable is set within the BIOS
U.2 Lane Distribution

U.2 (PU1) – x4 from Z390 PCH
o U.2 Enable/Disable is set within the BIOS
o This U.2 port shares lanes with the M.2 Key-M slot PM1. Installing a
U.2 device will disable PM1.