Technical Data
6.10 Digital In-/Outputs P6
Number
73
I/O-configuration
As input or output configurable pins of the FPGA
Input switching threshold LVTTL 3,3V or 2,5V LVDS switchable (see chapter “Coding Switches”
page 15), not 5V tolerant
Output current
Depending on FPGA configuration, see XILINX data sheet
Electrical isolation
None
Configuration
Single ended or differential, depending on FPGA configuration,
see Alternative Signal Names in chapter “PMC P4 I/O Connector”, from
page 29 and Xilinx documentation.
Protection circuit
None
Connector
P6 (XMC)
Table 15:
Data of the digital in-/outputs via P6
6.11 SATA
INFORMATION
The SATA interface is only available if P6 is equipped!
Number
1
Standard
Serial ATA 2.6 Specification
Data rate
1,5 Gbps and 3 Gbps
Topology
Serial ATA Controller
Electrical isolation
Via in-line capacitors
Software support
Driver of the operating system
Feature
- High-speed descriptor based DMA
- Native Command Queuing (NCQ)
Connector
P6 (XMC)
Table 16:
Data of SATA interface
6.12 Real-Time Clock (RTC)
Type
Epson RX8025SA
Connection
I
2
C Bus
Accuracy
+/-5 ppm at T
amb
= 25 °C (< 13 s/month)
Buffer
Goldcap, C = 0,8 F
Backup time
minimum 7 days at 25 °C
Table 17:
Data of RTC
Page 22 of 41
Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2
XMC-CPU/T10
