ESD V.2030.01, Руководство по оборудованию, Страница: 21 / 41

Technical Data
6.7 PMC Interface
Standard PMC according to IEEE Std 1386-2001 and IEEE Std 1386.1-2001
PCI bus PCI bus according to PCI Local Bus Specification 3.0,
32 bit 33/66 MHz, PCI bus master capability
Voltage 3.3 V, (5 V tolerant)
Frequency 33/66 MHz
Mode Monarch / non Monarch
Connector Via PMC P1, PMC P2
Device ID / Vendor ID Constant 0x082D / 0x1957
Table 12: Data of the PMC interface
6.8 XMC Interface
Standard XMC according to VITA 42.3, 4-lane PCI EXPRESS ® acc. to PCIe 1.1
(with T1022, T1042)
Lanes 4
Mode As device
Connector Via XMC P5
Device ID / Vendor ID Constant, 0x082D / 0x1957
Table 13: Data of the XMC interface
6.9 Digital In-/Outputs P4
Number 62x LVTTL-IO
I/O-configuration As input or output configurable pins of the FPGA
Input switching threshold LVTTL 3,3V or 2,5V LVDS switchable (see chapter “Coding Switches”
page 15), not 5V tolerant
Output current Depending on FPGA configuration, see XILINX data sheet
Electrical isolation None
Configuration Single ended or differential, depending on FPGA configuration,
see Alternative Signal Names in chapter “PMC P4 I/O Connector”,
from page 29 and Xilinx documentation.
Protection circuit None, current-limiting resistors are not provided.
Connector XMC-P4
Table 14: Data of the digital in-/outputs via P4
XMC-CPU/T10 Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2 Page 21 of 41