Overview
1. Overview
Figure 1:
Block circuit diagram
The XMC-CPU/T10 is a 64-bit XMC PowerPC Host CPU.
It is equipped with a PMC and an XMC interface.
The NXP
®
PowerPC
®
QorIQ
®
T1022 with 1.2 GHz features two 64-bit e5500 Power Architecture
®
processor cores with high performance data path acceleration architecture (DPAA) and network
peripheral interfaces.
The local memory bus is 64 bits wide plus 8 bits ECC with an overall capacity of 512 Mbyte.
16 Mbyte SPI Flash for boot loader and 32 Kbit I²C EEPROM for U-Boot environment offer non-
volatile memory spaces.
The XMC-CPU/T10 features a second 16 Mbyte 'fallback' SPI Flash, used for system recovery if a
system crash occurs during a firmware update. Alternatively it can be used for application software.
The Xilinx
®
FPGA Artix
®
-7 is connected to the CPU by local bus for low latency data exchange. For
high bandwidth data exchange the FPGA and the CPU are additionally connected via PCI
Express
®
. 62 LVTTL-I/Os of the FPGA are routed to the PMC-P4 connector.
The XMC interface comes with 4-lane PCIe bus and is designed according to VITA
TM
42.3.
The PMC interface supports 32 bit / 66 MHz PCI bus according to PCI Local Bus Specification 3.0.
The XMC-CPU/T10 provides two Gigabit Ethernet interfaces accessible at the front panel, which
give an excellent base for EtherCAT
®
applications.
The USB host port supports USB 2.0.
The Flash memory carries the standard boot program “Das U-Boot” and enables the XMC-
CPU/T10 to boot various operating systems from on-board Flash, network or USB.
BSPs are available from esd as described in the “Order Information” on page 40. The BSPs
include an example source code for the FPGA. Programming of the FPGAs is done via XILINX
Toolchain.
The esd EtherCAT
®
Master Stack is available for the BSPs developed by esd (see page 40).
XMC-CPU/T10
Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2
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