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 8.2.1 

GPIO Modules

.............................................................................................................37

9. 

Bootloader

.................................................................................................................................. 38

9.1 

License

................................................................................................................................ 38

9.2 

Configuration and Console Access

......................................................................................38

9.3 

Special Commands

..............................................................................................................39

10. 

Order Information

.....................................................................................................................40

Page 8 of 41

Hardware Manual • Doc. No.: V.2030.21 / Rev. 1.2

XMC-CPU/T10

Содержание V.2030.01

Страница 1: ...r Board with FPGA Hardware Manual to Product V 2030 01 XMC CPU T10 Hardware Manual Doc No V 2030 21 Rev 1 2 Page 1 of 41 esd electronics gmbh Vahrenwalder Str 207 30165 Hannover Germany http www esd e...

Страница 2: ...esd eu Internet www esd eu This manual contains important information and instructions on safe and efficient handling of the XMC CPU T10 Carefully read this manual before commencing any work and follo...

Страница 3: ...changes in the hardware as well as changes in the description of the facts only Rev Chapter Changes versus previous version Date 1 1 First released English manual 2016 12 07 1 2 3 Chapter restructure...

Страница 4: ...ements indicate a hazardous situation which if not avoided will result in death or serious injury WARNING Warning statements indicate a hazardous situation that if not avoided could result in death or...

Страница 5: ...ulated live parts with high voltages inside of the system into which the XMC CPU T10 is to be integrated All current circuits which are connected to the device have to be sufficiently protected agains...

Страница 6: ...d in an appropriate way or have to be returned to the manufacturer for proper disposal Please make a contribution to environmental protection Typographical Conventions Throughout this manual the follo...

Страница 7: ...Device Interface 20 6 7 PMC Interface 21 6 8 XMC Interface 21 6 9 Digital In Outputs P4 21 6 10 Digital In Outputs P6 22 6 11 SATA 22 6 12 Real Time Clock RTC 22 6 13 Health 23 6 14 Memory Interface...

Страница 8: ...1 GPIO Modules 37 9 Bootloader 38 9 1 License 38 9 2 Configuration and Console Access 38 9 3 Special Commands 39 10 Order Information 40 Page 8 of 41 Hardware Manual Doc No V 2030 21 Rev 1 2 XMC CPU...

Страница 9: ...ta exchange For high bandwidth data exchange the FPGA and the CPU are additionally connected via PCI Express 62 LVTTL I Os of the FPGA are routed to the PMC P4 connector The XMC interface comes with 4...

Страница 10: ...ilable on request as well as a Serial ATA interface CPU Type Furthermore other CPU types T1014 T1042 are applicable also an additional MRAM and other serial interfaces RS 232 via P4 Flash Up to 2x 128...

Страница 11: ...16 before starting the installation of the hardware See also page 25 and following for signal assignments of the connectors The JTAG connectors and the Debug interface connector have to be connected...

Страница 12: ...nterfaces X400 X1900 must be connected from the bottom side of the XMC CPU T10 See also page 25 and following for signal assignments of the connectors esd offers special adapters as accessories see Or...

Страница 13: ...Ds 0 4 3 1 2 Ethernet LEDs ETH1 ETH2 Each Ethernet interface comes with a green Activity LED and a yellow Link LED The LEDs are integrated in the RJ45 sockets of the Ethernet interfaces ETH0 and ETH1...

Страница 14: ...gure 3 page 12 LED Colour Indication Description LED on LED name in schematic diagram CON Activity green Activity Data transfer on terminal interface CON LED1222 USB PWR green Power 5 V power supply v...

Страница 15: ...ank 35 2 VCCO34 ON 3 3V I O voltage on FPGA Bank 34 OFF 2 5V I O voltage on FPGA for LVDS Bank 34 3 VCCO13 ON 3 3V I O voltage on FPGA Bank 13 OFF 2 5V I O voltage on FPGA for LVDS Bank 13 4 SPI_SEL E...

Страница 16: ...the XMC CPU T10 is to be integrated Disconnect all hazardous voltages mains voltage before opening the system If the system does not have a flexible mains cable but is directly connected to mains disc...

Страница 17: ...10 Connect the system to mains again mains connector or safety fuse 11 Switch on the system and the peripheral devices 12 End of hardware installation 13 Set the interface properties in your operating...

Страница 18: ...rt 2 64 pin PMC connector P4 PMC IO XMC Samtec ASP 103614 04 PCI Express interface XMC Samtec ASP 103614 04 e g 73 LVTTL or 34 LVDS I Os Only for test and programming purposes Debug Samtec CLM108 02 F...

Страница 19: ...TX 1000BASE T Bit rate 10 100 1000 Mbit s Connection Twisted Pair compatible to IEEE 802 3 Electrical isolation Via transformer 1500Vrms 2250 VDC Connector 2x at RJ 45 socket in the front panel Table...

Страница 20: ...opology Host Controller integrated in CPU Max current per port 5V 500 mA short circuit protected Electrical isolation None Software support OHCI Host controller and device driver driver of the operati...

Страница 21: ...D Constant 0x082D 0x1957 Table 13 Data of the XMC interface 6 9 Digital In Outputs P4 Number 62x LVTTL IO I O configuration As input or output configurable pins of the FPGA Input switching threshold L...

Страница 22: ...uit None Connector P6 XMC Table 15 Data of the digital in outputs via P6 6 11 SATA INFORMATION The SATA interface is only available if P6 is equipped Number 1 Standard Serial ATA 2 6 Specification Dat...

Страница 23: ...it sec Usage Das U Boot Image for the CPU Table 19 Data of the memory interface 6 15 Software Support The flash memory carries the standard boot program Das U Boot and enables the XMC CPU T10 to boot...

Страница 24: ...he license is contained in the esd document 3rd Party Licensor Notice as part of the product documentation esd provides the complete bootloader source code on request esd strives to restore all change...

Страница 25: ...ly voltage D D USB signal lines Data Data not connected GND Reference potential 7 2 CON USB Device X1220 Device connector 5 pin mini USB socket standard type B Pin Position Pin Assignment Pin CON X122...

Страница 26: ...I2 TP2 6 MDI1 TP1 7 MDI3 TP3 8 MDI3 TP3 S Shield Signal Description MDIx MDIx Ethernet data lines x 0 3 Shield case shield connected with the front panel of the XMC CPU T10 NOTICE Cables of category C...

Страница 27: ...11 GND 3 3 VAUX to battery 12 13 PCI CLK GND 14 15 GND GNT 16 17 REQ 5V 18 19 VIO AD 31 20 21 AD 28 AD 27 22 23 AD 25 GND 24 25 GND C BE3 26 27 AD 22 AD 21 28 29 AD 19 5V 30 31 VIO AD 17 32 33 FRAME...

Страница 28: ...D 26 22 23 AD 24 3 3V 24 25 IDSEL AD 23 26 27 3 3V AD 20 28 29 AD 18 GND 30 31 AD 16 C BE2 32 33 GND n c 34 35 TRDY 3 3V 36 37 GND STOP 38 39 PERR GND 40 41 3 3V SERR 42 43 C BE1 GND 44 45 AD 14 AD 13...

Страница 29: ...IO 13 3 3V or 2 5V IO LVDS_B35_23_N 15 FPGA IO 14 3 3V or 2 5V IO LVDS_B35_18_P 16 FPGA IO 15 3 3V or 2 5V IO LVDS_B35_23_P 17 FPGA IO 16 3 3V or 2 5V IO LVDS_B35_19_N 18 FPGA IO 17 3 3V or 2 5V IO LV...

Страница 30: ...8 FPGA IO 47 3 3V or 2 5V IO TxS1 RS232 O LVDS_B35_24_P 49 FPGA IO 48 3 3V or 2 5V IO CTSS1 RS232 I LVDS_B34_23_N 50 FPGA IO 49 3 3V or 2 5V IO RxS0 RS232 I LVDS_B34_22_N 51 FPGA IO 50 3 3V or 2 5V IO...

Страница 31: ...ND 8 n c JTAG_TDI 8 GND 8 GND 8 n c 8 n c 9 n c 9 n c 9 n c 9 n c 9 n c 9 GND 10 GND 10 n c JTAG_TDO 10 GND 10 GND 10 EEPROM_GA0 10 PCIe_Rx_L0p 11 PCIe_Rx_L0n 11 n c FPGA BIST 11 PCIe_Rx_L1p 11 PCIe_R...

Страница 32: ...GA IO 118 LVDS B35 15 P 11 FPGA IO 116 LVDS B35 15 N 11 FPGA IO 152 LVDS B13 11 N CLK Input 11 FPGA IO 119 LVDS B35 14 P CLK Input 11 FPGA IO 117 LVDS B35 14 N CLK Input 11 FPGA IO 153 LVDS B13 6 N 11...

Страница 33: ...rder No V 2029 02 is an interface to connect the Abatron BDI2000 or BDI3000 debugger to the XMC CPU T10 connector X900 Samtec CLM box header 16 pins 16 pins Figure 6 XMC CPU ADAPTER BDI NOTICE The 16...

Страница 34: ...CLM box header 16 pins 6 pins Figure 7 XMC CPU T10 ADAPTER NXP NOTICE The 16 pole SMD strip has no inverse polarity protection Property damage may result due to incorrect adapter connection Ensure th...

Страница 35: ...cope to the XMC CPU T10 connector X1900 Furthermore the adapter can be used to connect X400 to a JTAG chain of the Health Controller and PCIe to PCI bridge The connector X400 is for factory test only...

Страница 36: ...acturer NXP http www nxp com The CPU can access the Xilinx FPGA via a local bus or a PCIe bus 8 1 1 Access Addresses from CPU to FPGA Start address End address Description 0xFF00 0000 0xFF10 0000 Acce...

Страница 37: ...r Xilinx https www xilinx com A Sample FPGA for the I O configuration is included in delivery of the XMC CPU T10 With this Sample FPGA the following tables are valid Offset addresses of the modules fo...

Страница 38: ...After the next power on you will see the bootloader start up messages being output on the serial console When you see the message Press SPACE hit the space key to stop booting and to access the intera...

Страница 39: ...t_fpga 198 Initialize FPGA interface Net Fman1 Uploading microcode version 106 4 14 FM1 DTSEC4 PRIME FM1 DTSEC5 Hit any key to stop autoboot 0 9 3 Special Commands Command Description fpgaboot Program...

Страница 40: ...0 Linux BSP Linux Board Support Package incl 12 moths support V 2030 57 XMC CPU T10 QNX BSP QNX Board Support Package incl 12 moths support V 2030 55 XMC CPU T10 OS9 BSP OS 9 Board Support Package inc...

Страница 41: ...AT Master Stack for VxWorks Object code Runtime license for a single site P 4500 20 For detailed information about the driver availability for your special operating system please contact our sales te...

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