10. TIMING CHARACTERISTICS
S1D15722D01B000 Technical Manual (Rev.1.1)
EPSON
63
10.3 Serial Interface
t
SCYC(WR)
t
SCYC(RD)
t
CSS
t
CSH
t
SAS(WR)
t
r
*
1
t
SLW(WR)
t
SLW(RD)
t
SDS
SI
(Write)
SCL
A0
(Write)
CS
t
SAH(WR)
t
SHW(WR)
t
SHW(RD)
t
SDH
t
f
*
1
t
ACCS
t
OHS
t
SAS(RD)
A0
(Read)
t
SAH(RD)
SI
(Read)
Fig.10.3
Table 10.3
[V
DD
=3.0V to 5.5V, T
a
= -40 to +90
°
C]
Standard value
Item Signal
Symbol
Conditions
Min. Max.
Unit
Serial clock cycle
Write
SCL
t
SCYC
(WR)
250
-
ns
Read
t
SCYC
(RD)
450
-
SCL HIGH pulse width
Write
t
SHW
(WR)
50
-
Read
t
SHW
(RD)
250
-
SCL LOW pulse width
Write
t
SLW
(WR)
150
-
Read
t
SLW
(RD)
150
-
Address setup time
Write
A0
t
SAS
(WR)
50
-
Read
t
SAS
(RD)
50
-
Address hold time
Write
t
SAH
(WR)
50
-
Read
t
SAH
(RD)
50
-
Data setup time
SI
t
SDS
50
-
Data hold time
(Write)
t
SDH
50
-
___
CS -SCL time
___
CS
t
CSS
50
-
t
CSH
150
-
___
RD access time
SI
t
ACCS
Cloud = 100pF
150
-
Output disable time
(Read)
t
OHS
30 250
*1. The rising and trailing times (
t
r
and
t
f
) of the input signal are below 15 ns.
*2. All timings are stipulated on the basis of 20% and 80% of V
DD
.
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