Epson S1D15722 Series, Техническое руководство

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10. TIMING CHARACTERISTICS
60 EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Table 10.1
[V
DD
=3.0V to 5.5V, T
a
= -40 to +90
°
C]
Standard value
Item Signal Symbol Conditions
Min. Max.
Unit
Address hold time A0
t
AH8
0 - ns
Address setup time
t
AW8
150 -
System write cycle time
___
WR
t
WCYC8
1000 -
System write cycle time
___
CS
t
WCYC8C
1600 -
System read cycle time
___
RD
t
RCYC8
1600 -
System read cycle time
___
CS
t
RCYC8C
1600 -
Control L pulse width (
___
WR) ___
WR
t
CCLW
650 -
Control L pulse width (
___
CS )
___
CS
t
CCLWC
1000 -
Control L pulse width (
___
RD )
___
RD
t
CCLR
1000 -
Control L pulse width (
___
CS )
___
CS
t
CCLRC
1000 -
Control H pulse width (
___
WR) ___
WR
t
CCHW
350 -
Control H pulse width (
___
CS )
___
CS
t
CCHWC
600 -
Control H pulse width (
___
RD )
___
RD
t
CCHR
600 -
Control H pulse width (
___
CS )
___
CS
t
CCHRC
600 -
Data setup time D0 to D7
t
DS8
600 -
Data hold time (
___
WR)
t
DH8
30 -
Data hold time (
___
CS )
t
DH8C
100 -
___
RD access time
t
ACC8
Cload=100pF - 1000
Output disable time
t
OH8
50 600
*1. Accessed by
___
WR and
___
RD at
___
CS = LOW.
*2. Accessed by
___
CS at
___
WR,
___
RD = LOW.
*3. The rising and trailing times (
t
r
and
t
f
) of the input signal are below 15 ns. When the system cycle time is
used at high speed, stipulated at (
t
r
+
t
f
)
≤
(
t
CYC8
-
t
CCLW
-
t
CCHW
) or (
t
r
+
t
f
)
≤
(
t
CYC8
-
t
CCLR
-
t
CCHR
).
*4.
t
CCLW
and
t
CCLR
are stipulated by the overlap period when
___
CS is at LOW and
___
WR and
___
RD are at the
LOW level.
*5. All timings are stipulated on the basis of 20% and 80% of V
DD
.