Epson S1D15722 Series, Техническое руководство

Страница: 19 / 77

6. FUNCTIONAL DESCRIPTION
14 EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
Fig.6.1 Signal Chart of Serial Interface
* When the chip is inactive, the counter is reset to the initial state. Continuous serial clock input is possible,
however, it is recommended to clear the counter by setting
___
CS = HIGH for every 8 bits of serial clock at the
time of serial data input so that malfunction caused by external noise can be prevented. When reading serial
data, continuously read data by entering serial clock from the SCL pin with the setting left
___
CS = LOW
instead of setting
___
CS = HIGH after the read command. After getting the read data, to set
___
CS = HIGH is
necessary.
* For serial interface, read from display data RAM is not enabled.
* For SCL signal, great care should be taken for wiring termination reflection and external noise. It is
recommended to check operation using the actual equipment.
6.1.4 Chip Select
Since this IC has chip select pin, parallel interface or serial interface is enabled when
___
CS = LOW is set.
When the chip select is inactive, D0 to D7 are in the state of high impedance and input of A0,
___
RD,
___
WR, SI,
and SCL is disabled. When serial interface is selected, shift register and counter are reset.
6.1.5 Accessing Display Data RAM and Internal Register
Since this IC is accessed as a kind of pipeline processing between LSIs via bus holder coming with internal
data bus, wait time is not necessary if the cycle time is satisfied, enabling high-speed data transmission.
„
When writing serial data
CS
_____
SI
SCL
1 2 3 4 5 6 7 8 1 2 3 4 5 6
A0
„
When reading serial data
CS
_____
SI
SCL
A0
D7 D6 D5 D4 D3 D2 D1
D0
D7 D6 D5 D4 D3
D2
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Read status command
Output data