Epson S1D15722 Series, Техническое руководство

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10. TIMING CHARACTERISTICS
64 EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
10.4 Display Control I/O Timing
FR
CL
t
DFR
F1,F2
SYNC
t
DF1
,
F2
t
DSYNC
t
WHCL
t
CLF
t
r
t
f
t
WLCL
t
DSYNC
Fig.10.4
Table 10.4 Output timing
[V
DD
=3.0V to 5.5V, T
a
= -40 to +90
°
C]
Standard value
Item Signal Symbol Conditions
Min. Typ. Max.
Unit
FR delay time FR
t
DFR
CL = 50pF -200 - 200 ns
F1 and F2 delay time F1,F2
t
DF1,F2
-200 - 200
Use of built-in
oscillation circuit
(CLS = HIGH)
SYNC delay time SYNC
t
DSYNC
-200 - 200
FR delay time FR
t
DFR
0 - 500
F1 and F2 delay time F1,F2
t
DF1,F2
0 - 500
External input
(CLS = LOW)
SYNC delay time SYNC
t
DSYNC
0 - 500
Table 10.5 Input Timing
[V
DD
=3.0V to 5.5V, T
a
= -40 to +90
°
C]
Standard value
Item Signal Symbol Conditions
Min. Typ. Max.
Unit
FR delay time FR
t
DFR
-1.25 - 1.25
µ
s
F1 and F2 delay time F1,F2
t
DF1,F2
-1.25 - 1.25
µ
s
SYNC delay time SYNC
t
DSYNC
-1.25 - 1.25
µ
s
Input clock duty ratio
*
2
t
CLD
20 - 80 %
Input clock cycle
t
CLF
6.25 - -
µ
s
Input clock rise time (20% to 80%) * 3
t
r
- - 15 ns
Input clock fall time (20% to 80%) * 3
t
f
- - 15 ns
Low level pulse width
t
WLCL
1.25 - -
µ
s
High level pulse width
CL
t
WHCL
1.25 - -
µ
s
*1: All timings are stipulated on the basis of 20% and 80% of V
DD
.
*2: The CL duty ratio is stipulated by [%] 100
CLF
WHCL
CLD
t
t
t
×
=
or [%] 100
CLF
WLCL
CLD
t
t
t
×
=
.
*3 A signal beyond the specification has no problem for the functionality, but
t
CLF
,
t
WLCL
and
t
WHCL
always
should be kept.