6. FUNCTIONAL DESCRIPTION
S1D15722D01B000 Technical Manual (Rev.1.1)
EPSON
21
6.3 Oscillation Circuit
This CR-type oscillator generates internal clocks and display clocks. The oscillation circuit is enabled only
when set to M/S = HIGH and CLS = HIGH. Oscillation starts following input of the built-in oscillation circuit
ON command.
When set to CLS = LOW, oscillation stops and display clock is input from the CL pin.
6.4 Display Timing Signal Generator
Based on the built-in oscillation circuit or external clock, display timing signals (FR, SYNC, F1, F2, CL, and
____
DOF) are generated.
The FR normally generates 2-frame alternating drive system drive waveform to the liquid crystal drive circuit.
FR normally generates. Setting data a for the n-line inverted drive register generates n-line inversion alternating
drive waveform for each 4
×
(a+1) line. When the display quality such as cross talk presents a problem, it may
be improved by using the n-line inverted alternating drive. Determine the number of lines n for AC drive
through actual liquid crystal display.
When this IC is shared by multiple chips, supply the display timing signals (FR, SYNC, F1, F2, CL, and
____
DOF) to the slave from the master and synchronize the master and the slave.
The state of FR, SYNC, F1, F2, CL, and
____
DOF is shown in Table 6.5.
Table 6.5
Operating Mode
CL
FR, SYNC, F1, F2,
____
DOF
Built-in oscillation circuit enabled (CLS = HIGH)
Output
Output
Master (M/S = HIGH)
Built-in oscillation circuit disabled (CLS = LOW)
Input
Output
Built-in oscillation circuit enabled (CLS = HIGH)
Input
Input
Slave (M/S = LOW)
Built-in oscillation circuit disabled (CLS = LOW)
Input
Input
6.5 Operating State Detector Circuit
This circuit detects an error if the state of a specific command register was changed because of excessive
external noise. The circuit can determine the state at the level output from the pin ERR or read the state from
the data bus using the read status command.
Relationship between the output level from the pin ERR and the internal state is shown in Table 6.6.
Table 6.6
Output Descriptions
LOW
Error was not detected.
HIGH Bit-flip
occurred in part of the command register.
When the level is set to HIGH, display operation may not be normal because of bit-flip in the command
register. Monitor the level of the pin ERR or execute the read status command regularly to check the operating
state of the IC. When an error is detected, reset all the commands. It is also recommended to rewrite to all
the bits of the display data RAM concurrently with the above operation.
This circuit detects specific error modes. It does not support all command registers. For command
registers to be supported and expanded information, see 7.1 Command Description (30) Read Status. The
initial state after resetting is ERR = HIGH. This function is enabled after resetting.
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