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RX8010

SJ

Page

−

8

ETM37E-06

9.2.

Restrictions on Access Operations during Power-on Initialization and Recovery from Backup

•

RTC-register operations are linked to the internal quartz oscillator's clock signal, so normal operation is not

possible if there is no internal oscillation (= oscillation is stopped).

Therefore, we recommend that the initial setting to be set during power-on initialization or backup and restore
operations (i.e., when the power supply voltage is recovered after oscillation has stopped due to a voltage drop,
etc.) should be "first start internal oscillation, then wait for the oscillation stabilization time (see tSTA standard)

to

elapse".

•

Note the following caution points concerning access operations during power-on initialization or when restoring the

power supply voltage from backup mode (here after referred to as "switching to the operating voltage").

1) Before switching to the operating voltage, read the VLF-bit

(which indicates the RTC error status).

2) Initialization is required when the value read from the VLF-bit is "VLF

=

1

(error status)".

Before initializing in response to this VLF

=

"1"

result, we recommend first waiting for the internal oscillation

stabilization time

(see the tSTA standard) to elapse.

Initialization is required when the status after reading a VLF-bit value of "1"

is either of the following.

(Status 1)

During power-on initialization

(Status 2)

When the clock setting is invalid, such as due to a voltage drop during backup

∗

Access timing during power-on initialization and when recovering the power supply voltage after a drop in the

voltage used to maintain the clock

V

DD

Oscillation start voltage [v]

Internal oscillation

(illustration)

t

STA

[

s

]

Oscillation s tart time

(internal osc illation w ait time)

• Normal acc ess is enabled

• Normal operation is enabled

Min imum v oltage for clock maintenance V

CLK

(

Min.

)

[

V

]

During power-on initialization or power s upply
v ol tage recovery after drop in clock maintenance
v ol tage

40

[

ms

]

Note: After 40 (ms) has elaps ed, access is enabled.
However, access guarantee range is address 20h

∼

2F h.

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Содержание RX801SJ

Страница 1: ...ETM37E 06 Preliminary Application Manual Real Time Clock Module RX8010SJ ...

Страница 2: ...nd any technical information furnished if any for the development and or manufacture of weapon of mass destruction or for other military purposes You are also requested that you would not make the products available to any third party who may use the products for such prohibited purposes These products are intended for general use in electronic equipment When using them in specific applications th...

Страница 3: ...istics 7 Deleted a comment of Target spec 7 Deleted a software command of TS sample 20 21 Corrected a 13 3 Alarm interrupt Function 28 Corrected a setting data of Flow chart Ex2 ETM37E 04 06 Nov 2013 4 Corrected a Item of 7 Frequency Characteristics 6 Corrected a caution of 8 2 1 AC characteristics 1 ETM37E 05 13 Dec 2013 12 Changed a 12 2 Register table 34 Corrected a 13 8 7 The example of the co...

Страница 4: ...ation 9 11 Application notes 10 12 Overview of Functions and Description of Registers 11 12 1 Overview of Functions 11 12 2 Register table 12 12 3 Description of registers 13 13 How to use 15 13 1 Clock calendar explanation 15 13 2 Fixed cycle Timer Interrupt Function 15 13 3 Alarm Interrupt Function 20 13 4 Time Update Interrupt Function 23 13 5 Frequency stop detection function 25 13 6 FOUT func...

Страница 5: ...This is a real time clock module of the serial interface system that incorporates a 32 768 kHz crystal oscillator The real time clock function incorporates not only a calendar and clock counter for the year month day day of the week hour minute and second but also a time alarm interval timer and time update interruption among other features All of these many functions are implemented in a thin com...

Страница 6: ... pin outputs interrupt signals L level for alarm timer time update and FOUT This is an N ch open drain output IRQ2 Output This pin outputs interrupt signals L level for timer and FOUT This is a C MOS output VDD Supply This is a power supply pin GND Supply This pin is connected to a ground Note Input pins are able to input up to 5 5V regardless of VDD applied voltage Note Open drain pins are able t...

Страница 7: ...RX8010 SJ Page 3 ETM37E 06 4 External Dimensions 4 1 External Dimensions RX8010SJ SOP 8 pin External dimensions Unit mm 7 0 0 2 6 0 0 2 5 8 1 1 27 0 4 3 9 0 1 4 0 6 0 22 0 8 2 65 Max ...

Страница 8: ...P SDA IRQ1pin 5 5 V Operating temperature TOPR No condensation 40 25 85 C Minimum value of Clock supply voltage VCLK is the timekeeping continuation lower limit value that initialized RX8010 in operating supply voltage VACC 7 Frequency Characteristics Unless otherwise specified GND 0 V Ta 40 C to 85 C Item Symbol Condition Min Typ Max Unit Output frequency fo 32 768 Typ kHz Frequency stability f f...

Страница 9: ...sumption 4 IDD4 VDD 3 V 0 52 0 90 Current consumption 5 IDD5 fSCL 0 Hz IRQ1 OFF IRQ2 1024 Hz ON CL 15 pF VDD 5 V 0 45 1 10 µA Current consumption 6 IDD6 VDD 3 V 0 40 0 90 High level input voltage VIH SCL SDA pin 0 8 VDD 5 5 V Low level input voltage VIL SCL SDA pin GND 0 3 0 2 VDD V High level output voltage VOH1 IRQ2 pin VDD 5 V IOH 1 mA 4 5 5 0 V VOH2 VDD 3 V IOH 0 5 mA 2 7 3 0 Low level output ...

Страница 10: ...or SCL and SDA tf 0 3 0 3 µs Allowable spike time on bus tSP 50 50 ns Timing chart tHD DAT tSU DAT tHD STA tLOW tHIGH 1 fSCL tr tf tSU STA SDA SCL START CONDITION S BIT 7 MSB A7 BIT 6 A6 ACK A Protocol tBUF tSU STO STOP CONDITION P START CONDITION S P A tHD STA tSU STA S BIT 0 LSB R W S tSP Caution When communication of I 2 C bus is started consumption electric currents increase When accessing thi...

Страница 11: ... 2 Wait At least 40ms 3 Dummy read 1 4 Check VLF bit 1 5 Write 00 h Address Reg 1F h 6 Write 80 h Address Reg 1F h 7 Write D3 h Address Reg 60 h 8 Write 03 h Address Reg 66 h 9 Write 02 h Address Reg 6B h 10 Write 01 h Address Reg 6B h 11 Wait At least 2ms 2 END A disappearance of the FOUT output when the voltage sharply went up and down For example VDD voltage of the RX8010 is come and go between...

Страница 12: ... the VLF bit which indicates the RTC error status 2 Initialization is required when the value read from the VLF bit is VLF 1 error status Before initializing in response to this VLF 1 result we recommend first waiting for the internal oscillation stabilization time see the tSTA standard to elapse Initialization is required when the status after reading a VLF bit value of 1 is either of the followi...

Страница 13: ...cy deviation in any temperature α 1 C2 Coefficient of secondary temperature 0 035 0 005 10 6 C2 θT C Ultimate temperature 25 5 C θX C Any temperature 2 To determine overall clock accuracy add the frequency precision and voltage characteristics f f f fo fT fV f f Clock accuracy stable frequency in any temperature and voltage f fo Frequency precision fT Frequency deviation in any temperature fV Freq...

Страница 14: ... The reflow conditions within our reflow profile is recommended Therefore always check the mounting temperature and time before mounting this device Also check again if the mounting conditions are later changed See Fig 1 profile for our evaluation of Soldering heat resistance for reference 2 Mounting equipment While this module can be used with general purpose mounting equipment the internal cryst...

Страница 15: ...d 3 Long Timer function It is able to use fixed cycle timer interrupt function as Long Timer that deals with for approx 15 years 4 Alarm interrupt function The alarm interrupt function generates interrupt events for alarm settings such as date day hour and minute settings When an interrupt event occurs the AF bit value is set to 1 and the IRQ1 pin goes to low level to indicate that an event has oc...

Страница 16: ... 31 Reserved Setting data 0 0 0 0 1 0 0 0 32 IRQ Control TMPIN FOPIN1 FOPIN0 Setting data 0 0 0 0 0 TMPIN FOPIN1 FOPIN0 Note During the initial power on from 0 V and if the value of the VLF bit is 1 when the VLF bit is read be sure to initialize all registers before using them When doing this be careful to avoid setting incorrect data as the date or time as timed operations cannot be guaranteed if...

Страница 17: ...sible by a combination of FSEL bits select the frequency of clock output or inhibits the clock output Please refer to 13 6 FOUT Function for the details 2 USEL UF UIE bit This bit is used to specify either second update or minute update as the update generation timing of the time update interrupt function Please refer to 13 4 Update interrupt function for the details 3 TE TF TIE TSEL2 TSEL1 TSEL0 ...

Страница 18: ...by all means Writing data as follows Address h Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 17 Reserved Setting data 1 1 0 1 1 0 0 0 1F Control Register TEST STOP UIE TIE AIE TSTP Setting data 0 STOP UIE TIE AIE TSTP 0 0 Address h Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 30 Reserved Setting data 0 0 0 0 0 0 0 0 31 Reserved Setting data 0 0 0 0 1 0 0 0 32 IRQ Control TMP...

Страница 19: ...eek counter The day of the week is indicated by 7 bits bit 0 to bit 6 The day data values are counted as Day 01h Day 02h Day 04h Day 08h Day 10h Day 20h Day 40h Day 01h Day 02h etc It is incremented when carry is generated from the HOUR register This register does not generate carry to a higher register Since this register is not connected with the YEAR MONTH and DAY registers it needs to be set a...

Страница 20: ...ount value from 1 0001 h to 65535 FFFFh can be set Be sure to write 0 to the TE bit before writing the preset value When TE 0 read out data of timer counter is default Preset value And when TE 1 read out data of timer counter is just counting value But when access to timer counter data counting value is not held Therefore for example perform twice read access to obtain right data and a way to adop...

Страница 21: ...he result when a fixed cycle timer interrupt event is detected TF Data Description Write 0 The TF bit is cleared to zero to prepare for the next status detection Clearing this bit to zero does not enable the IRQ low output status to be cleared to Hi z 1 This bit is invalid after a 1 has been written to it Read 0 1 Fixed cycle timer interrupt events are detected Result is retained until this bit is...

Страница 22: ... the rising edge of the SCL ACK output signal that occurs when the TE value is changed from 0 to 1 TSEL0 TE TSEL2 TSEL1 Count down IRQ1 2 pin SDA Master SCL Internal timer WADA SDA Slave ACK 13 2 4 Fixed cycle timer interrupt interval example The combination of the source clock settings and fixed cycle timer countdown setting sets interrupt interval as shown in the following examples Timer Counter...

Страница 23: ...imer starts Fixed cycle timer stops After the interrupt event that occurs when the count value changes from 0001h to 0000h the counter automatically reloads the preset value and again starts to count down Repeated operation The count down that starts when the TE bit value changes from 0 to 1 always begins from the preset value TMPIN 1 0 IRQ1 16 bit counter TE Source clock 4096 Hz 64 Hz 1 Hz 1 60 H...

Страница 24: ... 0 1 Alarm registers Reg 18 h to 1A h In the WEEK alarm Day alarm register Reg 1A the setting selected via the WADA bit determines whether WEEK alarm data or DAY alarm data will be set If WEEK has been selected via the WADA bit multiple days can be set such as Monday Wednesday Friday Saturday 1 The register that 1 was set to AE bit doesn t compare alarm Example Write 80h AE 1 to the WEEK Alarm DAY...

Страница 25: ...of alarm settings when Week has been specified and WADA bit 0 Week is specified WADA bit 0 Week Alarm HOUR Alarm MIN Alarm bit 7 AE bit 6 S bit 5 F bit 4 T bit 3 W bit 2 T bit 1 M bit 0 S Monday through Friday at 7 00 AM Minute value is ignored 0 0 1 1 1 1 1 0 07 h AE bit 1 Every Saturday and Sunday for 30 minutes each hour Hour value is ignored 0 1 0 0 0 0 0 1 AE bit 1 30 h Every day at 6 59 AM 0...

Страница 26: ...on AIE bit IRQ1 output AF bit Event occurs 1 0 Hi z L 1 0 RTC internal operation Write operation Internal MIN Update AF Flag AIE IRQ1 MIN comparison result AF 0 Clear MIN AE HOUR AE WEEK DAY AE HOUR comparison result WEEK comparison result DAY comparison result 0 1 WADA ...

Страница 27: ...L bit Update Interrupt Select This bit is used to select second update or minute update as the timing for generation of time update interrupt events USEL Data Description Write 0 Selects second update once per second as the timing for generation of interrupt events 1 Selects minute update once per minute as the timing for generation of interrupt events 2 UF bit Update Flag This flag bit value chan...

Страница 28: ...rupt function diagram UIE bit IRQ1 output UF bit Carry tRTN period period period period 1 0 Hi z L 1 0 Operation in RTC Write operation tRTN 7 568 ms 15 625 ms Carry Sec F64Hz Update Control Circuit USEL bit UF 0 Clear Carry Min tRTN UF Flag UIE bit IRQ1 ...

Страница 29: ...cleared by zero 13 6 FOUT function clock output function The clock signal can be output via the IRQ1 IRQ2 pin When stopped the IRQ2 pin output the pin becomes the Hi z 13 6 1 FOUT control register Address h Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1D Extension Register FSEL1 FSEL0 USEL TE WADA TSEL2 TSEL1 TSEL0 Address h Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 32 I...

Страница 30: ...ording to your expectation please surely adjust according to conditions to use use environment 1 Processing example of the power on When an internal oscillation starts 0 writing of VLF is approved Start Wait Wait time of 40ms is necessary at least Whether it is a return from the state of the backup is confirmed VLF 1 YES YES NO VLF 0 clear Wait VLF 0 Software reset NO Please set waiting time depen...

Страница 31: ...rs Reg 18h to 1Ah can be used as a RAM register In such cases be sure to write 0 to the AIE bit Setting the Timer function Reg 1B h 1F h 32 h Set the fixed cycle Timer function When the fixed cycle timer function is not being used the fixed cycle timer register Reg 1B to 1C can be used as a RAM register In such cases stop the fixed cycle timer function by writing 0 to the TE and TIE bits When init...

Страница 32: ...P bit to 0 Reg 1D h Write 04 h Stop cancellation Reg 1F h Write 00 h Cancel STOP bit to 0 and start restart clock Setting the reserved bits Reg 17 h 30 h 32 h Reserved bits have to write in specified fixed value in the case of initialization by all means 3 The setting of a clock and calendar Next process START STOP 1 Set STOP bit to 1 to prevent timer update in time setting Write time Write inform...

Страница 33: ... to 0 to stop timer interrupt function The countdown period is fixed by the combination of the TSEL2 TSEL1 TSEL0 bit Reg 1E h Clear TF bit to 0 to cancel last timer interrupt output IRQ output Reg 1B h 1C h Set initial value of down counter Start count Set TE bit to 1 to start timer interrupt function When start timers interrupt function please surely set reset implement 2 initial value of down co...

Страница 34: ... of the Alarm interrupt function Next process START Reg 1F h Clear AIE bit to 0 to stop Alarm interrupt function Reg 18 h 1A h Set alarm data Reg 1F h Select and set IRQ1 output in AIE bit Reg 1D h Select week or day in WADA bit Reg 1E h Clear AF bit ...

Страница 35: ...dition 1 START condition The SDA level changes from high to low while SCL is at high level 2 STOP condition This condition regulates how communications on the I 2 C BUS are terminated The SDA level changes from low to high while SCL is at high level 3 Repeated START condition RESTART condition In some cases the START condition occurs between a previous START condition and the next STOP condition i...

Страница 36: ...I 2 C bus device CPU etc RX8010 SDA SCL VDD Master Transmitter Receiver Slave Transmitter Receiver Any device that controls the data transmission and data reception is defined as a Master and any device that is controlled by a master device is defined as a Slave The device transmitting data is defined as a Transmitter and the device receiving data is defined as a receiver In the case of this RTC m...

Страница 37: ...10 6 CPU transfers RESTART condition Sr in which case CPU does not transfer a STOP condition P 7 CPU transfers RX8010 s slave address with the R W bit set to read mode 8 Check for ACK signal from RX8010 from this point on the CPU is the receiver and the RX8010 is the transmitter 9 Data from address specified at 4 above is output by the RX8010 10 CPU transfers ACK signal to RX8010 11 Repeat 9 and 1...

Страница 38: ...ignal from RX8010 START Slave address 0 Write Address 20h SCL SDA Write data Write in A5h STOP CPU release the SDA line 2 Address specification read sequence When read A5h from address 20h ACK signal from RX8010 STRAT Slave address 0 Write Address 20h RESTRAT Slave address 1 Read SCL SDA Data of Address 20h A5h read STOP ACK from CPU CPU release the SDA line ...

Страница 39: ...ghai Branch High Tech Building 900 Yishan Road Shanghai 200233 China Phone 86 21 5423 5577 Fax 86 21 5423 4677 Shenzhen Branch 12 F Dawning Mansion 12 Keji South Road Hi Tech Park Shenzhen China Phone 86 755 2699 3828 Fax 86 755 2699 3838 Epson Hong Kong Ltd Unit 715 723 7 F Trade Square 681 Cheung Sha Wan Road Kowloon Hong Kong Phone 86 755 2699 3828 Shenzhen Branch Fax 86 755 2699 3838 Shenzhen ...

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