RX8010
SJ
Page
−
13
ETM37E-06
12.3. Description of registers
12.3.1. Clock and calender counter
(
Reg
-
10[h]
∼
16[h]
)
This is counter registers from a second to year.
∗
Please refer to [13.1
Clock calendar explanation ] for the details.
12.3.2. RAM registers
(Reg
-
20[h]
∼
2F[h]
)
This RAM register is read/write accessible for any data in the range from 00
h to FF
h.
12.3.3. Alarm registers
(
Reg
-
18[h]
∼
1A[h]
)
The alarm interrupt function is used, along with the AE, AF, and WADA bits, to set alarms for specified date, day,
hour, and minute values.
∗
Please refer to [13.3. Alarm Interrupt Function ] for the details.
12.3.4. Timer setting and Timer counter register
(
Reg
-
1B[h]
∼
1C[h]
)
This register is used to set the default (preset) value for the counter.
To use the fixed-cycle timer interrupt function,TE,
TF,
TIE,
TSEL2,TSEL1,
TSEL0,TMPIN bits are
set and used. When the fixed-cycle timer interrupt function is not being used, the fixed-cycle timer control register
can be used as a RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and
TIE bits.
∗
Please refer to [13.2. Fixed-cycle Timer Interrupt Function ] for the details.
12.3.5. Function-related register 1
(
Reg
-
1D[h]
∼
1F[h]
)
1) FSEL1, FSEL0 bit
A combination of the FSEL1 and
FSEL0 bits is used to select the frequency to be output.
The choice is possible by a combination of FSEL-bits select the frequency of clock output or inhibits the
clock output.
∗
Please refer to [13.6.
FOUT Function ] for the details.
2) USEL , UF, UIE bit
This bit is used to specify either "second update" or "minute update" as the update generation timing of
the time update interrupt function.
∗
Please refer to [13.4. Update interrupt function] for the details.
3) TE, TF, TIE, TSEL2, TSEL1, TSEL0, TSTP bit
These bits are used to control operation of the fixed-cycle timer interrupt function.
4) WADA, AF, AIE bit
These bits are used to control operation of the alarm interrupt function.
5)
TEST
bit
Those bits are the manufacturer's test bit. Always leave this bit value as "0"
except when testing.
6) VLF bit
This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to
"1" when data loss occurs, such as due to a supply voltage drop.
∗
Please refer to [13.5. Frequency stop detection function ] for the details.
7) STOP bit
This bit is to stop a timekeeping operation.
In the case of “STOP bit = 1", working is as follows a function .
∗
1)
All the update of timekeeping and the calendar operation stops.
With it, an update interrupt event does not occur at an alarm interrupt and the time.
∗
2) The part of the fixed-cycle timer interrupt function stops.
A count stops the source clock setting of the timer in case of "64Hz, 1Hz, 1min, 1h".
∗
3) Note 3: The effect of STOP bit to FOUT functions.
When STOP = "1", 32768Hz output is possible.
But 1Hz and 1024Hz output is disabled.
