E.F. Johnson Company 5100 Series, Руководство по обслуживанию

Страница: 48 / 173

CIRCUIT DESCRIPTION
5-21
5.10.4 TRANSMIT SIGNAL PATH
The ADSIC contains an analog-to-digital (ADC)
converter for the microphone. The microphone path in
the ADSIC also includes an attenuator that is
programmed by the microcontroller through the SPI
bus. The microphone input in the ADSIC is on pin
MAI (U2-75). The microphone ADC converts the
analog signal to a series of data words and stores them
in internal registers. The DSP accesses this data
through the parallel data bus. As with the speaker data
samples, the DSP reads the microphone samples from
registers mapped into its memory space. The ADSIC
provides an 8 kHz interrupt to the DSP on IRQB for
processing the microphone data samples.
The DSP processes these microphone samples
and generates and mixes the appropriate signaling and
filters the resultant data. This data is then transferred
to the ADSIC on the DSP SSI port. The ADSIC gener-
ates a 48 kHz interrupt so that a new sample data
packet is transferred at a 48 kHz rate and sets the
transmit data sampling rate at 48 ksps. These samples
are then input to a transmit D/A which converts the
data to an analog waveform. This waveform is the
modulation signal from the ADSIC and is connected to
the VCO on the RF Board.
5.10.5 ADSIC (U2)
The ADSIC is a complex custom IC which
performs many analog-to-digital, digital-to-analog,
and purely digital functions as previously described.
The ADSIC has four internal registers accessible by
the DSP. Two of these registers are read-only while the
two others are write-only. Therefore, they can be
accessed as two locations in the I/O spaces.
Crystal Y1 along with the internal oscillator in
the ADSIC provide a 20 MHz clock. This clock signal
is used internally by the ADSIC and is also multiplied
by two to provide a 40 MHz clock to the DSP. The
frequency of the clock can be electronically shifted a
small amount by controlling varicap D1 through the
OSCW pin (U2-16). This removes interference created
on some channels by the clock.
The ADSIC and DSP exchange the sampled
receive data and the sampled VCO modulation signal
through a serial port. This serial port consists of pins
SCKR, RFS, RxD, TxD, SCKT, and TFS on the
ADSIC.
SDO is the output of the internal speaker DAC.
MAI is the input of the internal microphone attenuator
and is followed by the microphone ADC.
The ADSIC is configured partially by the DSP
through its data and address bus. However, most of the
configuring is provided through an SPI compatible
serial bus. This SPI serial bus consists of pins SEL*,
SPD, and SCLK.
5.11 AUDIO CIRCUIT (VERSION A/B)
NOTE: The following describes the Version A and B
logic described in Section 1.13.
5.11.1 RECEIVE AUDIO CIRCUIT
NOTE: A block diagram of the audio circuit is shown
in Figure 5-5.
In receive mode, the analog receive waveform
created by ADSIC U2 (on the Logic Board) is fed out
of that device on the SDO (Signal Data Out) pin. It is
then converted to a differential signal by U8C and
U8D to minimize noise. The signal is then fed to the
UI board on the Audio_Out_P/M lines and converted
back to a single-ended signal by U17B. It is then
combined by U17C with any tones from U17A and
applied to the audio amplifiers.
Audio amplifier U8 provides amplification for the
internal 8-ohm speaker and U21 provides amplifica-
tion for an external speaker-microphone connected to
pins 2 and 6 of the accessory (UDC) connector. U8
and U21 provide 750 mW of power with an 8-ohm
load.
The gain of U8 and U21 is controlled by the DC
voltage on the Vin (3) pin. When this pin is grounded
by mute switches Q10 or Q2, no output is produced.
Gain then increases as this DC voltage increases. The
volume control signal is produced as follows:
The top panel volume control produces a varying
DC voltage that is buffered by U20 on the UI board.
This voltage is then applied to A/D converter U9 and
LOGIC BOARD (VERSION A/B) AUDIO CIRCUIT (VERSION A/B)