E.F. Johnson Company 5100 Series, Руководство по обслуживанию

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CIRCUIT DESCRIPTION
5-20
ADSIC via the serial port. In the ADSIC, the VCO D/
A converts the sampled modulation signal into an
analog signal and then routes this signal to the VCO
on the RF Board.
5.10.3 RECEIVE SIGNAL PATH
The ABACUS IC on the RF Board provides a
digital back end for the receiver section. It provides a
digital output of I (in phase) and Q (quadrature)
samples which represent the IF signal at the receiver
back end. These samples are routed to the ADSIC
where the signal is filtered and frequency discrimi-
nated to recover the modulating signal.
The recovered signal is sent to the DSP chip for
processing. The ADSIC interface to the ABACUS is
comprised of four signals SBI, DIN, DIN*, and ODC.
SBI is a programming data line for the ABACUS.
This line is used to configure the operation of the
ABACUS and is driven by the ADSIC. Microcon-
troller U2 programs many of the ADSIC operational
features through the SPI interface. There are 36
configuration registers in the ADSIC of which 4
contain configuration data for the ABACUS. When
these particular registers are programmed by the
microcontroller, the ADSIC in turn sends this data to
the ABACUS through the SBI.
DIN and DIN* are the data lines in which the I
and Q data words are transferred from the ABACUS.
These signals make up a differentially encoded current
loop. Instead of sending TTL-type voltage signals, the
data is transferred by flowing current one way or the
other through the loop. This helps reduce internally
generated spurious emissions on the RF Board. The
ADSIC contains an internal current loop decoder
which translates these signals back to TTL logic and
stores the data in internal registers.
The ODC signal is a clock the ABACUS provides
to the ADSIC. Most internal ADSIC functions are
clocked by this ODC signal at a rate of 2.4 MHz and
are available as soon as the power is supplied to the
circuitry. This signal initially may be 2.4 or 4.8 MHz
after power-up. It is programmed by the ADSIC
through the SBI signal to 2.4 MHz when the ADSIC is
initialized by the microcontroller through the SPI bus.
For any functionality of the ADSIC to exist, including
initial programming, the reference clock must be
present.
In the fundamental operating mode, the ADSIC
transfers raw IF data to the DSP. The DSP then
performs IF filtering and discriminator functions to
produce a baseband demodulated signal. However, the
ADSIC also includes a digital IF and discriminator
function and can provide a baseband demodulated
signal directly to the DSP. This is typically what
occurs. The digital IF filter is programmable by the
microcontroller with up to 24 taps.
The DSP processes this data through the SSI
serial port. This is a six-port synchronous serial bus.
The ADSIC transfers the data on the TxD line to the
DSP at a rate of 2.4 MHz. This is clocked synchro-
nously by the ADSIC which provides a 2.4 MHz clock
on SCKT. In addition, a 20 kHz interrupt is provided
on TFS to signal the arrival of a data packet. This
means a new I and Q sample data packet is available to
the DSP at a 20 kHz rate which represents the
sampling rate of the received data. The DSP then
processes this data to extract audio, signaling, and
other information based on the 20 kHz interrupt.
In addition to the SPI programming bus, the
ADSIC also contains a parallel configuration bus. This
bus is used to access registers mapped into the DSP
memory. Some of these registers are used for addi-
tional ADSIC configuration controlled directly by the
DSP. Some of the registers are data registers for the
speaker D/A. Analog speaker audio is processed
through this parallel bus where the DSP outputs the
speaker audio digital data words to this speaker D/A.
In addition, an analog waveform is generated which is
output to SDO (Speaker Data Out).
In conjunction with speaker D/A, ADSIC
contains a programmable attenuator to set the rough
signal attenuation. However, the fine levels and differ-
ences between signal types are adjusted through the
DSP software algorithms. The speaker D/A attenuator
setting is programmed by the microcontroller through
the SPI bus.
The ADSIC provides an 8 kHz interrupt to the
DSP on IRQB for processing the speaker data
samples. This 8 kHz signal must be enabled through
the SPI programming bus by the microcontroller and is
necessary for any audio processing to occur.
LOGIC BOARD (VERSION A/B)