E.F. Johnson Company 5100 Series, Руководство по обслуживанию

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CIRCUIT DESCRIPTION
5-4
IF of 64.455 MHz to a second IF frequency of 2.1
MHz. Phase Locked Loop circuitry inside of the
AD9864 operates with a phase-detector frequency
of 15 kHz.
Second Conversion Mixer and Filtering - A mixer
inside the AD9864 converts from the first IF of
64.455 MHz to the second IF of 2.1 MHz. External
filters (L29 and L30) provide IF bandpass filtering.
Additional filtering is provided by the inherent
operation of the sigma-delta analog/digital
converters.
Gain Control - This device provides up to 12 dB of
AGC range via a combination of analog and digital
controls. Additionally, there is a 16 dB attenuator
in the front end. The optimum settings are
controlled by the host microprocessor.
Analog/Digital Conversion and Processing -
Sigma-delta converters provide I and Q sampling
directly from the second IF frequency. The
resulting digital words are first filtered by internal
programmable FIR filters and then clocked out of
the AD9864 via a serial data bus using a program-
mable data rate.
5.2.2 SYNTHESIZER
The following three phase locked loops are used
in the VHF radio module to provide the required
overall functionality and performance levels.
Receive PLL
The receive PLL provides a signal that is in the
frequency range of 200 to 239 MHz. In receive mode
it is programmed for a frequency that is 64.455 MHz
above the receive frequency. In transmit mode it is
programmed for a frequency that is equal to 374.4
MHz minus the desired transmit frequency.
Transmit PLL
The transmit PLL phase locks a transmit oscil-
lator that is operating at an output frequency of 138 to
174 MHz. The RF signal into the PLL chip is created
by mixing the transmit frequency with the receive PLL
frequency to generate a mix frequency of 374.4 MHz.
This provides low frequency modulation of the VCO
by modulating the transmit PLL reference frequency.
Reference PLL
The reference PLL phase locks the receive PLL
reference oscillator to the transmit PLL reference
oscillator with a loop bandwidth of less than 10 Hz.
This PLL ensures that the center frequency of both
reference oscillators are the same. It also limits the
modulation of the receive PLL reference oscillator by
the low frequency modulation applied to the transmit
PLL reference oscillator.
PLL IC
Two CX72301 sigma-delta modulated PLL chips
(U29 & U46) are used for the PLLs described above.
This PLL chip provides good phase noise capabilities
to reduce adjacent channel interference and quick
switching between the receive and transmit modes.
Reference Oscillators
One 16.8 MHz oscillator (Y1) is used as the
frequency reference for the receive PLL and also for
the receiver backend IC.
The other 16.8 MHz oscillator (Y2) is used as the
frequency reference to the transmit PLL. The center
frequency of this oscillator is corrected using a DC
tuning voltage from the digital board in the receive
mode and it is modulated with voice or data in the
transmit mode.
The receive PLL reference oscillator is phase
locked to the transmit PLL reference oscillator as
discussed above.
Analog Switches and PLL Loop Filters
An analog switch (U17) provides faster switching
of signals during channel changes by varying the time
constant of the PLL loop filter.
5.2.3 TRANSMITTER
Modulation
A “dual-port” modulation scheme is used to
provide the DC coupling of the signal required for data
modulation applications. In this scheme, modulation
applied to the transmit PLL frequency reference
provides low-frequency modulation, and modulation
VHF RF BOARD (VERSION C)