E.F. Johnson Company 5100 Series, Руководство по обслуживанию

Страница: 36 / 173

CIRCUIT DESCRIPTION
5-9
LNA minimizes the impact of the filter loss on the
receiver sensitivity.
Mixer and LO Filter
A double-balanced, low-level ADEX-10L mixer
(MX1) with a LO drive of +4 dBm is used for the first
conversion. This mixer provides good dynamic range
with 3 dB lower LO drive than the more tradi7
dBm drive mixers. This provides power savings and
reduces conducted and radiated LO leakage from the
receiver. A high-side mix is used for the 700 MHz
receive band and a low-side mix is used for the 800
MHz receive band. This band plan reduces the tuning
range requirements for the VCOs.
A LO filter (including W1 and W2) is used prior
to LO port of the mixer to reduce the effect of wide-
band noise from the LO synthesizer on the receiver
sensitivity. This filter is varactor-tuned with the center
frequency tuned via a voltage from a D/A converter.
IF Filter and Amplifier
A four-pole 64.455 MHz crystal filter (U2) is
used to provide the desired level of adjacent channel
and image rejection while providing minimal ampli-
tude and phase distortion within the 25 kHz band-
width. Shields are installed around the crystal filter to
provide sufficient isolation in order to meet the second
image response requirements and minimize noise
pickup by the impedance-matching inductors (L1, L2
and L7.)
A transistor IF amplifier (Q1 and supporting
circuitry) is used to boost the signal strength which
reduces the overall noise figure. The noise figure,
signal gain, intercept point and power consumption are
optimized by this circuit. An LC circuit provides the
required impedance matching between the output of
the IF amplifier and the input of backend chip U11.
Back End IC
An Analog Devices AD9864 IF Digitizing
Subsystem IC (U11) provides the following receiver
functions:
Second Local Oscillator - A varactor-tuned tran-
sistor (Q2) oscillator is phase-locked to a fixed
frequency of 62.355 MHz in order to convert the
first IF of 64.455 MHz to a second IF frequency of
2.1 MHz. Phase Locked Loop circuitry inside of
the AD9864 operates with a phase-detector
frequency of 15 kHz.
Second Conversion Mixer and Filtering - A
mixer inside the AD9864 converts from the first IF
of 64.455 MHz to the second IF of 2.1 MHz.
External filters L29 and L30 provide IF bandpass
filtering. Additional filtering is provided by the
inherent operation of the sigma-delta analog/digital
converters.
Gain Control - This device provides up to 12 dB
of AGC range via a combination of analog and
digital controls. Additionally, there is a 16 dB
attenuator in the front end. The optimum settings
are controlled by the host microprocessor.
Analog/Digital Conversion and Processing -
Sigma-Delta Converters provide I and Q sampling
directly from the second IF frequency. The
resulting digital words are first filtered by internal
programmable FIR filters and then clocked out of
the AD9864 via a serial data bus using a program-
mable data rate.
5.4.2 SYNTHESIZER
PLL IC
A CX72301 sigma-delta modulated PLL (U29) is
used as the main receive and transmit synthesizer. This
PLL chip provides exceptional phase noise capabilities
to reduce adjacent channel interference and quick
switching between the receive and transmit modes.
In the receive mode the PLL is programmed to a
Local Oscillator frequency that is 64.455 MHz from
the receive frequency. For the 700 MHz receive band,
the LO frequency is higher than the receive frequency,
and for the 800 MHz band, it is lower than the receive
frequency. In transmit mode, the PLL is programmed
directly to select the desired transmit frequency.
Reference Oscillator
A 16.8 MHz oscillator (Y1) provides the
frequency reference for the synthesizer and receiver
700/800 MHz RF BOARD (VERSION C)