D
Y
4 S
YSTEMS
I
NC
.
812628 V
ERSION
1 O
CTOBER
2003
VII
L
IST
OF
T
ABLES
Table 1.1:
Maximum CCA Mass .............................................................................................1-5
Table 1.2:
Dimensions of the SCP/DCP-122 ............................................................................1-5
Table 1.3:
SCP/DCP-122 Board Current Requirements..............................................................1-6
Table 2.1:
Jumper Settings Summary ....................................................................................2-2
Table 2.2:
Boot Flash Write Protect Jumper ............................................................................2-4
Table 2.3:
Application Flash Write Protect Jumper....................................................................2-5
Table 2.4:
PABS Flash Write Protect Jumper ...........................................................................2-6
Table 2.5:
Enable Booting from PABS Memory.........................................................................2-7
Table 2.6:
Watchdog Timer Power-up Behaviour .....................................................................2-8
Table 2.7:
User Link Configuration.........................................................................................2-9
Table 2.8:
Backup FPGA Boot PROM Select ........................................................................... 2-10
Table 4.1:
Serial Channel 1 RS-232 Connector (BPK-122-000 J3) Pinout.....................................4-4
Table 4.2:
Serial Channel 2 RS-232 Connector (BPK-122-000 J6) Pinout.....................................4-4
Table 4.3:
USB Connector (BPK-122-000 J4) Pinout.................................................................4-4
Table 4.4:
Ethernet Connector (BPK-122-000 J5) Pinout...........................................................4-5
Table 4.5:
DIO Header Pinout ...............................................................................................4-6
Table 4.6:
EIA-422 Channel 3 Pinout .....................................................................................4-7
Table 4.7:
EIA-422 Channel 4 Pinout .....................................................................................4-7
Table 4.8:
Transition Module P0 Row A Signal Mapping .......................................................... 4-10
Table 4.9:
Transition Module P0 Row B Signal Mapping .......................................................... 4-11
Table 4.10:
Transition Module P0 Row C Signal Mapping .......................................................... 4-12
Table 4.11:
Transition Module P0 Row D Signal Mapping .......................................................... 4-13
Table 4.12:
Transition Module P0 Row E Signal Mapping........................................................... 4-14
Table 4.13:
Foundation Firmware Execution Sequence ............................................................. 4-15
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