SCP/DCP-122 G
ETTING
S
TARTED
M
ANUAL
D
Y
4 S
YSTEMS
I
NC
.
4-18
812628 V
ERSION
1 O
CTOBER
2003
Summary;: Pass
Pass: Pass
Cpu Space Decode; : Pass
EPROM transfer: Pass
RAM data convergence: Pass
RAM address convergence: (0x0003ABD4-0x0003BB70) Pass
RAM misaligned transfer: Pass
RAM read/write: (0x0003ABD4-0x0003BB70) Pass
UART Reset Condition: Pass
UART Controllable bits: Pass
UART Loopback: Pass
UART Reset Condition: Pass
UART Controllable bits: Pass
UART Loopback: Pass
Base Card Common CSR RESET: Pass
Base Card Common CSR Controllable bits: Pass
Base Card-Specific CSR RESET: Pass
Base Card-Specific CSR Controllable bits: Pass
RAM data convergence: Pass
RAM misaligned transfer: Pass
RAM read/write: (0xF4008000-0xF400FFEC) Pass
Partition checksum: Pass
ISP1160 Reset Condition: Pass
ISP1160 Controllable bits: Pass
ISP1160 Reg Data Convergence Test: Pass
FPGA Timer Run Test: Pass
FPGA Timer INT Test: Pass
L2 RAM Data Test: Pass
L2 RAM Address Test: Pass
L2 Cache Miss Test: Pass
PCI Ven/Dev ID (0x80000000) expect 0x643011AB: Pass
GT64260 Ethernet Reset Condition: Pass
GT64260 Ethernet Controllable bits: Pass
GT64260 Ethernet Loopback: Pass
GT64260 Ethernet Loopback Ext: Pass
BCM5221 Reset Condition: Pass
BCM5221 Controllable bits: Pass
GT64260 ECC Polled: Pass
GT64260 ECC Interrupt: Pass
Temperature Sensor Reset: Pass
Temperature Sensor Controllable bits: Pass
Start-up PBIT Binary DRT address: 0x59C0
Diag Sub Result Progress Fail a Fail b Fail c Fail d
Cbm 0 Pass 0 0 0 0 0
RAM 0 Pass 0 0 0 0 0
Start-up PBIT ASCII DRT address: 0x6F00
CLD complete: 2 diagnostics were executed
Summary;: Pass
CBOOT Checksum Check: Pass
CBOOT Format Check: Pass
RAM size Check: Pass
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