D
Y
4 S
YSTEMS
I
NC
.
P
RODUCT
O
VERVIEW
812628 V
ERSION
1 O
CTOBER
2003
1-3
Figure 1.2 illustrates the architecture and major components of the SCP/DCP-122.
F
IGURE
1.2: SCP/DCP-122 Functional Block Diagram
Cross Reference
Please refer to Chapter 1 of the SCP/DCP-122 Hardware User’s Manual, document number
812629, for a detailed description of each of the functional blocks in the above diagram.
Latch
J2 Conn.
Power
Conversion
CPU-PCI
Bridge
DISCO I
SDRAM + ECC
128/256MB
4 x 16M x 16
Adr
Ctrl
Data
Transformer
termination
32/64 bit
33/66 MHz
5/3.3 Volt
FPGA
BP_5V
BP_3.3V
Power
Sequencer
BP_5V
BP_3.3V
BP_VIO
1.4V
1.8V
2.5V
5V
3.3V
VIO
PMC
Conn.
PN1,2,3
J1
Conn.
PMC
Conn.
PN4
termination
10/100
transceiver
RS232
transceiver
422
Xceivers
I/O Mux
Scheme
IBM750FX
512K L2 Cache
800MHz
DH
DL Adr Ctrl
CPU I/F
PCI 0
I/F
PCI 1
I/F
SDRAM
I/F
Ethernet
I/F
Serial
I/F
I2C I/F
MPP
I/F
Device I/F
Clocks
Temp
Sensor
Flash
Bank 0
32MBytes
Flash
Bank 1
32MBytes
USB Host
Controller
PABS
32 bit
33/66 MHz
5/3.3 Volt
Non-Muxed I/O
Pins
Muxed
I/O
Pins
100
MHz
25
MHz
66
MHz
6
MHz
Buffer
A
D
[24:
3]
Device Bus AD[31:0] & BADDR[2:0]
DEV_DATA [31:0]
31
:0
31
:0
15
:0
Peripheral Bus [7:0]
NVRAM/
RTC
DUART
M
P
S
C
I/
F
RS-232
CH2
[63:0]
[12:0]
[31:
0]
[31:
0]
[31:
0]
10/100BASE-TX ETHERNET
SEEPROM
Device AD [27:4] & Device BADDR[2:0]
Debug Port
40
MHz
COPS I/F
DIO[15:0]
ISP Prom
OTP Prom
Production Test
JTAG I/F
RS-232 CH1
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com