Digital Equipment AXPpci 33, Руководство по конструкции

Страница: 37 / 98

Physical Description
Figure 2–8 Speaker Circuit
MR-6406-AI
2.2.3 Device Sockets
The following sections describe the MLB device sockets. Sockets allow
the system integrator to easily add components specifically designed for
the MLB. These components include the cache SRAM devices and the
DECchip 21066 processor.
CAUTION: Correct installation of these parts is critical. Significant damage
results if these parts are not installed as specified in Appendix D.
2.2.3.1 AXPpci 33 Processor Socket (XE15)
The DECchip 21066 processor is installed in a 287-position ZIF socket
(XE15). Refer to Appendix D for installation and handling instructions.
2.2.3.2 Cache Sockets (XE100–XE110)
The AXPpci 33 MLB can operate without cache or with an optional
256 KB or 1 MB of cache using either 11 32K x 8 or 11 128K x 8 SRAM
devices. On power up, the CPU automatically determines the cache
size. Cache devices are socketed to allow easy installation by the system
integrator. Appendix A lists tested SRAM part numbers and associated
vendors.
Cache sockets can accept either 28-pin (32K x 8) or 32-pin (128K x 8)
SRAM devices. All devices must be of the same size and vendor. See
Section 2.2.4.1 for information about cache speed selection, and Section D.4
for cache installation instructions.
Note: If cache is used, it must be installed to fill all 11 sockets,
XE100–XE110. Provisions for error correction and detection
require 352 KB to have 256 KB user accessible, and 1.408 MB to
have 1 MB user accessible.
Figure 2–9 shows the cache socket.
CAUTION: The SRAM devices must be installed in the correct orientation
with regard to pin 1; otherwise, significant damage results. Use
either 0 or 11 devices.
2–19