Elektra CPU User Manual V1.00
Page 40
Base + 0
Read
A/D LSB
Bit
No. 7 6 5 4 3 2 1 0
Name
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
AD7 - 0
A/D data bits 7 - 0; AD0 is the LSB; A/D data is an unsigned 16-bit value.
The A/D value is derived by reading two bytes from Base + 0 and Base + 1 and applying the
following formula:
A/D value = (Base + 0 value) + (Base + 1 value) * 256
The value is interpreted as a twos complement 16-bit number ranging from –32768 to +32767.
This raw A/D value must then be converted to the corresponding input voltage and/or the
engineering units represented by that voltage by applying additional application-specific formulas.
Both conversions (conversion to volts and then conversion to engineering units) may be
combined into a single formula for efficiency.
Base + 1
Write
Enhanced Feature Key
Bit
No.
7 6 5 4 3 2 1 0
Name 1 0 1 0 0 1 1/0
1/0
Writing 0xA5 to this register enables the enhanced features of the register map.
Writing 0xA6 to this register disables the enhanced features of the register map. Upon disabling
the enhanced features, the “page” should return to 0, and the SE/DIFF and ADUNIP signals
should become inputs.
When enhanced features are disabled, the FPGA should act 100% identical to the Prometheus
FPGA. To simplify FIFO behavior, writing to this register can also be considered a FIFO reset (so
that the FIFO is in a known state upon transition.) It should be noted that this is an empty register
in the Prometheus map, so theoretically there should be no accesses to this register by programs
designed for the Prometheus.
Base + 1
Read
A/D MSB
Bit
No. 7 6 5 4 3 2 1 0
Name
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8
AD15 - 8
A/D data bits 15 – 8; AD15 is the MSB; A/D data is an unsigned 16-bit value.
See Base + 0 Read on the previous page for information on A/D values and
formulas.
