Elektra CPU User Manual V1.00
Page 51
Page 0, Base + 15
Read FPGA Revision Code
Bit
No. 7 6 5 4 3 2 1 0
Name
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
This register is used to control the counter/timers. A counter is selected with bit 7, and then a 1 is
written to any ONE of bits 6 – 0 to select the desired operation for that counter. The other bits and
associated functions are not affected. Thus only one operation can be performed at a time.
REV7-0
Revision code, read as a 2-digit hex value, i.e. 0x20 = revision 2.0
