Elektra CPU User Manual V1.00
Page 45
Base + 6
Write
DAC LSB
Bit
No. 7 6 5 4 3 2 1 0
Name
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
DA7–0
D/A data bits 7 - 0; DA0 is the LSB. D/A data is an unsigned 12-bit value. This
register must be written to before Base + 7, since writing to Base + 7 updates the
DAC immediately.
Base + 6 (A)
Read
A/D Channel and FIFO Status
Bit
No. 7 6 5 4 3 2 1 0
Name
0
0 FD5 FD4 FD3 FD2 FD1 FD0
FD5–0
Current FIFO depth. This value indicates the number of A/D values currently stored
in the FIFO.
Base + 6 (B)
Read
A/D Channel and FIFO Status
Bit
No. 7 6 5 4 3 2 1 0
Name 0 0 0 0
OVF
FF
HF
EF
They are enabled when EXPFIFO=1. If EXPFIFO=0, Base+6 acts like the base+6 (A).
EF Empty flag:
1 FIFO
is
empty
0
FIFO is not empty
HF Half full flag:
1
FIFO is at least half full; The FIFO contains 512 words, so if this flag is set the FIFO
contains at least 256 words of A/D data
0
FIFO is less than half full
FF Full flag:
1
FIFO is full; the next A/D conversion will result in an overflow
Chapter 1 FIFO is less than full
