DDC Total-AceXtreme BU-67301B, Руководство по конструкции

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H O S T I N T E R F A C E
Data Device Corporation DS-BU-67301B-G
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Synchronous Timing Information
Table 9 lists the 12 single-word Synchronous mode timing diagrams, Figure 23
through Figure 35. Table 10 lists the ten Synchronous burst timing diagrams, Figure
37 through Figure 46. Table 11 lists the timing parameters that are applicable for
these diagrams.
6.4.4.2 Synchronous Timing Information
Table 9. Single-Word Synchronous Transfers
Non-Multiplexed
or Multiplexed
Address/Data
32-bit or 16-bit Read or Write Memory or Register Timing Diagram
Non-Multiplexed 32 Read Memory Figure 23
Non-Multiplexed 32 Read Register Figure 24
Non-Multiplexed 32 Write Memory or Register Figure 25
Non-Multiplexed 16 Read Memory Figure 26
Non-Multiplexed 16 Read Register Figure 27
Non-Multiplexed 16 Write Memory Figure 28
Non-Multiplexed 16 Write Register Figure 29
Multiplexed 32 Read Memory Figure 30
Multiplexed 32 Read Register Figure 31
Multiplexed 32 Write Memory or Register Figure 32
Multiplexed 16 Read Memory Figure 33
Multiplexed 16 Read Register Figure 34
Multiplexed 16 Write Memory Figure 35
Multiplexed 16 Write Register Figure 36
Table 10. Synchronous Burst Transfers
Non-Multiplexed or
Multiplexed
32-bit or
16-bit
Sequential
or Random
Register or
Memory
Read or
Write
Timing Diagram
Non-Multiplexed 32 Sequential Memory Read Figure 37
Non-Multiplexed 32 Sequential Memory or
Register
Write Figure 38
Non-Multiplexed 32 Random Memory or
Register
Write Figure 39
Non-Multiplexed 16 Sequential Memory Read Figure 40
Non-Multiplexed 16 Sequential Memory or
Register
Write Figure 41