X64-AN Quad User's Manual
Theory of Operation
35
Sync on Separate Sync
In this mode the VS and HS signals are each input to the X64-AN Quad. The sync extractor circuit is
not used. The PLL compares the separate horizontal sync input to the internal feedback and generates
the PLL clock. The ADC uses the PLL clock to digitize the video input. The polarity of the sync inputs
can be negative or positive. The incoming signals must be referenced to system ground.
Analog Composite
Video
Pixels
Valid Pixels
ADC
LUT
Cropper
PLL
Pixel Clock
Cam
HS
VS
Figure 17: Separate Sync Video Synchronization Block Diagram
Each camera has its own VS and HS output which are typically TTL level.
Sapera parameters for Sync on Separate Sync:
CORACQ_PRM_SYNC = CORACQ_VAL_SYNC_SEP_SYNC
CORACQ_PRM_HSYNC: Size of horizontal sync pulse
CORACQ_PRM_HSYNC_POLARITY = CORACQ_VAL_ACTIVE_LOW or
CORACQ_VAL_ACTIVE_HIGH
CORACQ_PRM_HBACK_PORCH: Size of horizontal back porch
CORACQ_PRM_HACTIVE: Number of valid pixels per line
CORACQ_PRM_HFRONT_PORCH: Size of horizontal front porch
CORACQ_PRM_VSYNC: Size of vertical sync pulse
CORACQ_PRM_VSYNC_POLARITY = CORACQ_VAL_ACTIVE_LOW or
CORACQ_VAL_ACTIVE_HIGH
CORACQ_PRM_VBACK_PORCH: Size of vertical back porch
CORACQ_PRM_VACTIVE: Number of valid line from camera
CORACQ_PRM_VFRONT_PORCH: Size of vertical front porch
