Cypress FX2LP, Начало работы

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Application Note 6 of 42 001-65209 Rev.*I
2021-03-19
Getting Started with FX2LP™
FX2LP Introduction
Pipe
(FIFO)
SIE
P
H
Y
V
BUS
D+
D
-
GND
480 Mbits/sec
Figure 2 USB Connection to a Data Pipe
To handle the USB host side, FX2LP includes:
•
A physical bus interface (PHY) containing a USB 2.0 transceiver that supports Hi-Speed and Full Speed USB
transfers.
•
A Smart serial interface engine (SIE). The SIE translates PHY signals into bytes. All Cypress USB SIEs add logic
to handle low-level USB details, such as error correction and Packet ID (PID) synchronization, relieving the
programmer of these tasks. This Smart SIE delivers bytes to an endpoint FIFO memory. The Smart SIE also
contains logic to enumerate FX2LP as a full-fledged USB device and also capable of loading code into its
internal RAM.
•
Seven endpoints that support all four USB transfer types: CONTROL, BULK, INTERRUPT, and ISOCHRONOUS.
An endpoint is a transmitter or receiver of USB data.
•
Large endpoint buffers (FIFOs) with multiple buffering. Double, triple, or quad buffering allows USB transfers
to be pipelined with a peripheral, increasing the throughput.
•
Low- power operation (the “LP” in FX2LP). The USB VBUS wire supplies 5 V, which provides limited power to
peripheral devices. The low-power consumption of FX2LP enables you to create bus-powered applications.
For example, the FX2LP Development Kit is bus-powered, eliminating the need for an external power unit.
FX2LP can also be used in self-powered designs in which the peripheral device supplies its own power.
3.1.2 Parallel interfaces
The USB 2.0 specification and generous FX2LP buffering take care of transporting bytes in and out of endpoint
FIFOs at high speed over the USB interface, but that is only half of the job. The other end of the pipe must
transport the FIFO data on and off chip at speeds matching USB transfer rates. FX2LP contains two hardware
interfaces specifically designed for this purpose: Slave FIFO and general programmable interface (GPIF), as
shown in
Figure 1 .
Note: In addition to the high-speed transfer logic, the FX2LP 8051 has random access to the endpoint
FIFOs for applications that require interpreting or modifying the data that is moving between the
USB and peripheral interfaces.
3.1.2.1 Slave FIFO
FX2LP provides a Slave FIFO interface for use by external devices containing a FIFO controller, such as an MCU,
FPGA, or ASIC (see
Figure 3 ).
Pipe
(FIFO)
S
la
v
e
F
IF
O
L
o
g
ic
Data
Clock
Flags
Control
FIFO Address
Figure 3 FX2LP Slave FIFO Interface