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Application Note

9 of 42

001-65209 Rev.*I

2021-03-19

Getting Started with FX2LP™

FX2LP Introduction

PC[7:0]/GPIFADR[7:0]
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT

CTL[5:3]

RDY[5:2]

TxD1

RxD0

TxD0

RxD1

INT4

INT5#

WR#

RD#

CS#
OE#
PSEN#

A[15:0]

D[7:0]

100

128

PD[7:0]

PB[7:0]

RDY0
RDY1

CTL0
CTL1
CTL2

XTALIN
XTALOUT

DPLUS
DMINUS

SCL
SDA

RESET#
WAKEUP#

XCLK
CLKOUT

INT0#/PA0

PA1/DA0

PA2

WU2/PA3

PA4
PA5
PA6
PA7

IORDY
DMARQ

IOW
IOR
DMACK

←INTRQ
→DA0
→DA1
→DA2
→CS0
→CS1
→DASP
→RESET

FIFO Data

GPIF

SLRD
SLWR

PRGFLAG
INFULL
OUTEMPTY

←INT0
←INT1
←SLOE
PA3
←FIFOADR0
←FIFOADR1
←PKTEND
PA7

FIFO Data

Slave FIFO

Single Chip

Figure 5

Three FX2LP Package Choices

The 56-pin package is the lowest-cost version of FX2LP. The signals on the left edge of the 56-pin block (in

Figure 5

)

are common to all package versions in the family. Three modes are available in all package versions:

single-chip, GPIF, and Slave FIFO. These modes define the signals shown on the right edge of the 56-pin block
(in

Figure 5

). The 8051 selects the interface mode using an internal register. Single-chip mode is the power-on

default configuration.

The 100-pin package adds functionality to the 56-pin package by adding 44 pins:

•

Two additional 8-bit I/O ports, PORTC and PORTE.

•

Seven additional GPIF controls (CTL) and ready (RDY) signals.

•

Nine non-multiplexed control signals (two UARTs, three timer inputs, INT4, and INT5#).

•

Eight additional control signals multiplexed on to PORTE.

•

Nine GPIF address lines, multiplexed on to PORTC(8) and PORTE(1),

•

RD# and WR# signals, which may be used as read and write strobes for PORTC.

The 128-pin package adds 8051 address and data buses and their control signals. These added pins allow
FX2LP to operate with an external 8051 memory. This package is used in the FX2LP Development Board.

Содержание FX2LP

Страница 1: ...15A 16A 53 Associated project Yes Software version None More code examples We heard you To access a variety of FX2LP code examples please visit our USB High Speed Code Examples webpage To access USB 3 0 product family please visit our USB 3 0 Product Family webpage Table of contents About this document 1 Table of contents 1 1 Introduction 3 1 1 Bulkloop_FX2LP Project 3 1 1 1 VS_Control Center 3 1 ...

Страница 2: ... 3 2 Cypress USB Firmware Frameworks 20 5 3 2 1 TD_Init 22 5 3 2 2 TD_Poll 22 5 3 2 3 Interrupt Service Routines 23 5 3 2 4 Handling USB Dual Speeds 23 5 3 3 Building the Bulkloop Project 24 5 4 GPIF Designer 25 6 The Windows Side 27 6 1 Cypress USB Driver 27 6 1 1 Driver Library Alternatives 27 6 2 Cypress Libraries 28 7 Summary 30 8 Appendix A FX2LP Development Kit DVK 31 8 1 Firmware Example Pr...

Страница 3: ...velopment Environment IDE compiles the user code and USB Firmware Framework to produce the hex file This hex file needs to be loaded by the provided USB Control Center application and exercised by the provided Bulkloop_VCS application As part of the firmware tools discussion the GPIF Designer program is introduced to show how custom interfaces are created using graphical waveform entry see GPIF De...

Страница 4: ...ks Full speed devices operate at 12 Mbps to support higher bandwidth devices such as printers and disk drives A minor specification revision 1 1 released in 1998 mostly addressed hub issues and became the widely adopted first generation specification The USB 2 0 specification was released in 2000 It increased the signaling rate to 480 Mbps naming it Hi Speed The 2 0 specification is compatible wit...

Страница 5: ... interfaces In systems where the FX2LP CPU is not required to modify the data before sending it to the USB host the FX2LP firmware only needs to initialize its hardware transfer units allowing high bandwidth USB transfers to proceed without CPU intervention FX2LP can be programmed to enumerate as any USB device type conforming to a standard USB class such as HID or mass storage or a custom device ...

Страница 6: ...LP The USB VBUS wire supplies 5 V which provides limited power to peripheral devices The low power consumption of FX2LP enables you to create bus powered applications For example the FX2LP Development Kit is bus powered eliminating the need for an external power unit FX2LP can also be used in self powered designs in which the peripheral device supplies its own power 3 1 2 Parallel interfaces The U...

Страница 7: ...efore FX2LP provides a high speed interface GPIF shown in Figure 4 which provides direct connection to common interfaces such as disk drives FPGAs and ASICs without requiring additional glue logic The GPIF s core is a state machine you must develop waveforms using GPIF Designer to control the state machine The GPIF is driven by one of the four Waveform Descriptors which are data structures contain...

Страница 8: ...AM The enhanced interrupt system uses an Autovector mechanism to automatically call one of the 27 USB interrupt service routines ISRs depending on the USB activity that requires service Automatically incrementing pointer hardware Autopointers speed up block transfers 3 3 2 Boot Options FX2LP uses RAM for program storage FX2LP has the following boot options USB boot I2 C boot Boot from external par...

Страница 9: ...5 are common to all package versions in the family Three modes are available in all package versions single chip GPIF and Slave FIFO These modes define the signals shown on the right edge of the 56 pin block in Figure 5 The 8051 selects the interface mode using an internal register Single chip mode is the power on default configuration The 100 pin package adds functionality to the 56 pin package b...

Страница 10: ...5 Designing with EZ USB FX2LP Slave FIFO Interface using FPGA which presents a detailed design example Refer to KBA222479 USB2 0 Camera Interface Using FX2LP and Lattice CrossLink FPGA for an example project that implements a UVC framework to interface an image sensor with the Host PC mobile phone using the FX2LP device Some interface chips may provide the necessary FIFO interface signals without ...

Страница 11: ...FPGA Boots from External Memory At power on an FPGA boots its configuration bitstream using an external memory Figure 7 FPGA FX2LP PC Bitstream Figure 8 FPGA Boots through FX2LP FX2LP can be configured to load the FPGA bitstream file from the PC as in Figure 8 This eliminates the need for a boot memory and enables FPGA updates from the PC 3 4 4 Further Reading For an example implementation using a...

Страница 12: ...ng and Troubleshooting the Keil Debugger Environment Application note AN42499 Serial UART Port Debugging of FX1 FX2LP Firmware Application note AN58009 Host PC Software USB2 0 driver cyusb sys Available with Suite USB installation This Suite USB installation file exe is also available with the FX2LP DVK installation Suite USB for Mac OS is also available Use FX3 SDK for Linux to get the host appli...

Страница 13: ...com id 193 rtID 76 Reference Designs http www cypress com id 193 rtID 201 Knowledge Base Articles http www cypress com id 193 rtID 118 Material on USB 2 0 http www beyondlogic org usbnutshell usb1 shtml AN57294 USB 101 An Introduction to Universal Serial Bus 2 0 Third party Development Kits http www ztex de usb fpga 1 http www opalkelly com products xem6010 Features of these development kits are g...

Страница 14: ...EPROM that is connected to FX2LP The FX2LP firmware framework and the steps to build the FX2LP firmware are described in the FX2LP Firmware Development section 3 Use the Control Center application to program the RAM of FX2LP or the EEPROM that is connected to FX2LP Usage of the Control Center application is shown in the Using USB Control Center section 4 Verify the functionality of the firmware wi...

Страница 15: ...the first time follow these steps 1 Prepare FX2LP board jumpers as shown in Table 3 Table 3 EZ USB FX2LP Board Jumper Settings JP State Purpose 6 7 OUT Memory is configured for development 2 IN Power the board from USB connector 1 5 10 IN Local 3 3V power source 3 IN All 4 jumpers IN activate 4 LEDs D2 D5 8 Either Not used for Remote Wakeup testing 2 In the lower left corner of the board move the ...

Страница 16: ...d automatically detaches itself from USB and then re attaches as the device defined by the loaded hex file ReNumerationTM If the loaded hex file has custom Vendor ID VID and Product ID PID then you need to add these values to the Cypress inf file Cypress Driver cyusb sys PC bulkloop hex Figure 13 USB Control Center Loads Hex Files into the FX2LP Development Board Further Reading For more informati...

Страница 17: ... action FX2LP has enumerated twice first as a code loader and then as the loaded device The LED D5 should blink 8 times per second for a Hi Speed USB attachment and once per second for a Full Speed attachment You can observe this by looking at the toggling frequency of the LED D5 present on the FX2LP DVK For Hi Speed USB attachment you ll see the LED blink slowly for a second or so and then start ...

Страница 18: ...ch as controlling the LEDS and 7 segment readout on the FX2LP Development Board and using endpoint interrupts This code is examined in detail in the FX2LP Firmware Development section cyusb sys PC FX2LP EP2 OUT EP6 IN Figure 16 USB Control Center Tests the Bulkloop Firmware 1 Expand the Bulkloop Example tree view in the Control Center to reveal the implemented BULK endpoints Figure 17 Figure 17 Bu...

Страница 19: ... type 1234 The hex values display in the Data to send box and the Bytes to Transfer box increments for every digit typed Click the Transfer Data OUT button 5 In the Text to send box type abcdefg then click the Transfer Data OUT button 6 Select the Bulk in endpoint and leave the default Bytes to Transfer value of 512 bytes Click the Transfer Data IN button twice to read the two packets of data that...

Страница 20: ... in code size to 4096 bytes Cypress demo projects such as bulkloop uv2 fit under this limit so you can study and modify the code Larger projects require purchasing the full uVision2 toolset from Keil 5 3 2 Cypress USB Firmware Frameworks In conjunction with the Keil tools Cypress provides a set of files called the USB Firmware Frameworks to handle low level USB details This approach allows you to ...

Страница 21: ...ming various housekeeping steps it calls an external function called TD_init which you provide in bulkloop c The prefix TD stands for Task Dispatcher Then it enters an endless loop that checks for arrival of SETUP packets over CONTROL endpoint 0 The loop also checks for the USB suspend event but this is not used by the bulkloop application Every time through the loop it calls the external TD_Poll ...

Страница 22: ...ree interrupts SOF EP2 and EP6 endpoint interrupts 5 3 2 2 TD_Poll TD_Poll is called in an infinite loop residing in fw c Error Reference source not found For the bulkloop application only two tasks are required 1 Update the 7 segment readout with the number of packets waiting for transmission to the host The FX2LP register EP6CS Endpoint 6 Control and Status provides this number in bits 6 4 Furth...

Страница 23: ...numeration process This is a good time to initialize application hardware The I2 C unit that drives the 7 segment readout is initialized here EP2INOUT EP6INOUT ISR These IRQs fire when a packet is dispatched from EP6 IN or arrives at EP2 OUT The ISR code turns on an LED on the FX2LP Development Board then sets an inblink EP6 IN or outblink EP2 OUT variable in bulkloop c to control how long the LED...

Страница 24: ...t In the FX2LP Bulkloop Firmware folder double click the bulkloop uv2 file This opens the uVision2 IDE and loads the bulkloop project To compile and link the project click the Rebuild All Target Files button Figure 24 uVision2 IDE This creates the bulkloop hex file you downloaded in previous sections Note the following when installing Keil uVision2 Sometimes files unzipped from a web download inst...

Страница 25: ...s as Figure 26 shows Figure 26 GPIF Designer Block Diagram Tab The GPIF has six Control CTL outputs and six Ready RDY inputs that you can rename in the block diagram by right clicking in the RDY or CTL text blocks Your names propagate through GPIF Designer appearing as choices for state machine decision points and waveform names Figure 27 GPIF Waveform Entry Creates States Figure 27 shows a GPIF D...

Страница 26: ... the Status line click on the dotted clock line at the beginning of the decision state GPIF Designer inserts a diamond to signify the decision state Right clicking this diamond brings up a dialog box that allows you to create a logic equation using two variables and three logical operators AND OR XOR for the branch condition An unconditional branch is created by selecting the same state as destina...

Страница 27: ...SB device classes The driver is ideal for communicating with a vendor specific device from a custom USB application or for sending low level USB requests to any USB device for experimental or diagnostic applications Operating systems platforms supported by the driver are Windows XP Windows Vista and Windows 7 on both 32 and 64 bit versions If you modify the inf file for example to include your com...

Страница 28: ...x and how to build and integrate user written applications with the library FX2LP can also be programmed to be compliant with a standard Windows class for example Human Interface Device HID Communications COMM device or Mass Storage MSC device The Cypress web site has example FX2LP programs for these common classes The advantage of conforming to a Windows class is that no driver installation is re...

Страница 29: ...g this high level model is a great improvement over multiple Win32 API calls such as DeviceIOControl An excellent way to gain familiarity with the Cypress library is to open the Bulkloop_VCS solution using Microsoft Visual C Express edition and inspect the code Further Reading For more information on developing host applications refer to the application note AN70983 Designing a Bulk Transfer Host ...

Страница 30: ...xtensive suite of support collateral to help with each step of your design cycle This application note first introduced FX2LP then introduced Cypress hardware firmware and software tools by stepping through the design creation and testing of a BULK transfer example This example can serve as a basis for your custom application About the Author Name Rama Sai Krishna Title Application Engineer Senior...

Страница 31: ... from USB as in this application note or the code can be programmed into an onboard EEPROM When developing hardware for USB 2 0 Hi Speed devices board layout and design are critical to the success of the project To help developers avoid common layout errors Cypress provides several resources to help design a new board Application notes AN1168 and AN15456 give design guidelines for FX2LP In additio...

Страница 32: ...ts EP6IN always returns a 512 byte packet when operating at Hi Speed and 64 bytes when operating at Full Speed Based on buffer availability in EP8IN the most recent packet of EP4OUT is written to EP8IN 5 dev_io Source files to build simple development board I O sample This software demonstrates how to use the buttons and LEDs on the EZ USB development kit 6 EP_Interru pts Bulk loopback firmware us...

Страница 33: ...1 65209 Rev I 2021 03 19 Getting Started with FX2LP Appendix A FX2LP Development Kit DVK Note These software resources are continuously improved Therefore Cypress recommends downloading the latest software from the Cypress website ...

Страница 34: ... a low power programmable USB to SLC NAND controller Its programmability allows designers to include special features in the controller along with NAND device support an advantage over fixed controllers The hardware ECC engine present in NX2LP Flex supports 1 bit error correction and 2 bit error detection SX2 The EZ USB SX2 CY7C68001 is a programmable device designed to work with any external mast...

Страница 35: ...aller than a credit card at 75 mm x 50 mm x 15 9 mm 2 95 x 1 97 x 0 63 Self powered by external DC source Multi PLL multi output clock generator Cypress CY22393 2 FPGA FX2LP board from ZTEX More details of these boards can be found in the following location http www ztex de usb fpga 1 Features of one such board from ZTEX Cypress CY7C68013A EZ USB FX2LP Microcontroller Hi Speed 480 Mbps USB interfa...

Страница 36: ... It describes how to create read and write waveforms using GPIF Designer This application note is also useful as a reference to connect FX2LP to other SRAMs AN58009 Serial UART Port Debugging of FX1 FX2LP Firmware This application note describes the code needed in the FX2LP firmware for serial debugging This code enables the developer to print debug messages and real time values of variables in a ...

Страница 37: ...This application note describes a host application built on the MAC OS platform that uses libusb The host application Cocoa application communicates with the BULK IN and BULK OUT endpoints ofFX2LP using the interfaces provided by the APIs of libusb This host application implements the transfer with devices that pass the particular VID PID 0x04B4 0x1004 identification AN58764 Implementing a Virtual...

Страница 38: ...signs This reference design kit is based on the Cypress FX2LP and Legend Silicon s chipset A captured and demodulated RF signal converted to an MPEG2 TS stream by the Legend Silicon chipset is sent to the PC through an FX2LP The PC plays these streams using a media player This is a complete design including all required files ...

Страница 39: ...en cyusbfx1_fx2lp inf file Because this is a text file you can use any text editor such as WordPad Add your custom VID and PID as shown in Figure 31 and Figure 32 The steps shown in these figures assume the custom VID is 0x4B4 and PID is 0x1005 Note that these steps are shown for a Windows XP 32 bit platform Figure 31 Adding Custom VID and PID to Cyusb inf Figure 32 Adding custom VID and PID to Cy...

Страница 40: ...Application Note 40 of 42 001 65209 Rev I 2021 03 19 Getting Started with FX2LP Appendix E Adding Custom VID and PID to the inf File Figure 33 Custom FX2LP device listed in USB Control Center ...

Страница 41: ...n to list popular applications of FX2LP Added Before You Start and About the Design sections Restructured the entire application note Added Appendices A B C D and E D 2013 12 11 Rewrote the entire application note for better clarity E 2015 01 27 Included details on CyUSB Suite for Linux Removed reference to obsolete Specs Added link to USB Hi Speed Code Examples Updated template Sunset review F 20...

Страница 42: ...ntellectual property rights of any third party with respect to any and all information given in this application note The data contained in this document is exclusively intended for technically trained staff It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in th...

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