Cypress FX2LP, Начало работы

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Application Note 10 of 42 001-65209 Rev.*I
2021-03-19
Getting Started with FX2LP™
FX2LP Introduction
3.4 Example Applications of FX2LP
3.4.1 Interfacing FPGA/ASIC using Slave FIFO
In Figure 6 , an FPGA or ASIC contains a FIFO controller that connects directly to the FX2LP Slave FIFO pins. The
FPGA/ASIC also connects to hardware that is specific to the application, such as a data logger or image sensor.
Although a synchronous FIFO is shown using the IFCLK signal, FX2LP also supports an asynchronous (no clock)
FIFO interface.
System
sensors,
data
channels
etc.
FPGA
ASIC
FX2
LP
S
y
n
c
S
la
v
e
F
IF
O
PC
IFCLK
RD-WR-OE-CS
FLAGS
FIFOADR(2)
D(16/8)
PKTEND
U
S
B
2
.0
Figure 6 FPGA/ASIC Sees FX2LP as a FIFO
Further Reading
For more information about the FX2LP Slave FIFO interface, refer AN61345 - Designing with EZ- USB FX2LP™
Slave FIFO Interface using FPGA , which presents a detailed design example.
Refer to KBA222479 USB2.0 Camera Interface Using FX2LP™ and L attice CrossLink FPGA for an example
project that implements a UVC framework to interface an image sensor with the Host PC/mobile phone using
the FX2LP device.
Some interface chips may provide the necessary FIFO interface signals without modification. For example, an
MPEG decoder can map its signals to the FX2LP FIFO as follows:
Table 1 MPEG Decoder Connections to FX2LP
MPEG Decoder Signals FX2LP Signals
MPEG_CLK IFCLK
MPEG_SYNC PKTEND#
MPEG_VALID SLWR#
D[7:0] FD[7:0]
External Tuner Control I
2
C bus
3.4.2 Further Reading
Cypress provides a reference design for a “TV Dongle”, documented at FX2LP DMB-T / H TV Dongle Reference
Design .
If an external chip does not exactly map to the FX2LP Slave FIFO signals, as in Table 1 , the FX2LP GPIF can be
programmed to match the required signals without additional external logic.