CY8CKIT-040 PSoC
®
4000 Pioneer Kit Guide, Doc. # 001-91316 Rev. *F
109
Advanced Topics
7. Build the project by choosing
Build > Build Project
or pressing
[Shift] [F6]
. After the project is
built without errors and warnings, program (
[Ctrl] [F5]
) this code onto the PSoC 4 through the
PSoC 5LP programmer or MiniProg3.
Note:
A warning may be displayed on the I
2
C input clock. This is because to generate a 100-kbps
I
2
C clock, the block needs a 1.6-MHz signal, which cannot be derived from the default HFCLK
setting of 12 MHz. To remove the warning, go to
<project_name>.cydwr
>
Clocks
and double-
click
HFCLK
. Set the
IMO
to
32 MHz
and
HFCLK divider
to '
2
' in the window that appears (see
). This generates a 16-MHz HFCLK; using a divider of 10, the 1.6-MHz clock required
for I
2
C block will be generated.
Figure 6-7. Clock Settings in cydwr File
8. Open BCP from
Start > All Programs > Cypress > Bridge Control Panel <version number>
.
Содержание CY8CKIT-040 PSoC 4000 Pioneer Kit
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