Cypress CY3274, Руководство пользователя

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24 CY3274 Cypress High Voltage Programmable PLC Development Kit Guide, Doc. # 001-53598 Rev. *G
Kit Operation and PLC Control Panel GUI
3.1.1.1 Powerline FSK Modem PHY
The heart of the CY8CPLC20 device is the frequency shift keying (FSK) modem. The FSK
modulator sends digital data through two distinct frequencies; one frequency represents a digital 1
and the other represents a digital 0 (see
Figure 3-2 ). The FSK demodulator must receive the
transmitted analog signals and demodulate them to determine the correct sequence of 1s and 0s.
Figure 3-2. Sample FSK Waveform
Note: This diagram is only for conceptual understanding and is not to scale.
3.1.1.2 Powerline Network Protocol Stack
The network protocol that runs on the processor supports
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Bidirectional half-duplex communication
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Master-slave or peer-to-peer network topologies
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Multiple masters on powerline network
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Addressing
❐
8-bit logical addressing supports up to 256 Powerline nodes
❐
16-bit extended logical addressing supports up to 65536 Powerline nodes
❐
64-bit physical addressing supports up to 264 Powerline nodes
❐
Individual broadcast or group mode addressing
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Carrier Sense Multiple Access (CSMA)
The protocol provides the random selection of a period between 85 and 115 ms (out of seven
possible values in this range) in which the band-in-use (BIU) detector must indicate that the line
is not in use, before attempting a transmission.
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Band-In-Use (BIU)
A BIU detector, as defined under CENELEC EN 50065-1, is active whenever a signal that
exceeds 86 dB µVrms anywhere in the range 131.5 kHz to 133.5 kHz is present for at least 4 ms.
This threshold can be configured for different end-system applications not requiring CENELEC
compliance. The modem tries to retransmit after every 85 to 115 ms when the band is in use. The
transmitter times out after 1.1 seconds to 3.5 seconds (depending on the noise on the Powerline)
and generates an interrupt to indicate that the transmitter was unable to acquire the Powerline.
Note that for non-CENELEC compliant systems, the BIU interval can be modified for improved
performance by modifying the Timing_Config register. Refer the PLT UM datasheet for more
details.
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Verifies address and packet integrity (CRC) of received packets
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Transmits acknowledgments after receiving a valid packet, and automatically retransmits if a
packet is dropped.
0 1 0 0 0 1 1 1
Data
Modulated
Signal