56
CY3274 Cypress High Voltage Programmable PLC Development Kit Guide, Doc. # 001-53598 Rev. *G
Code Examples
Note
The above settings can also be done with the following application code, as shown below:
/* Set the baud rate to 2400bps with a 3kHz deviation */
PLT_Memory_Array[Modem_Config] = (Modem_FSKBW_3M | Modem_BPS_2400);
/* Enable the PLC Transmitter and Receiver*/
PLT_Memory_Array[PLC_Mode] = (TX_Enable | RX_Enable);
/* Enable Acknowledgement and 3 retries*/
PLT_Memory_Array[TX_Config] = (TX_Service_Type |
0x03
);
/* Set the transmitter gain to 1.55Vp-p.*/
PLT_Memory_Array[TX_Gain] =
0x0b
;
/* Set the receiver gain to 250uVrms */
PLT_Memory_Array[RX_Gain] =
0x06
;
/* Set the length of the transmit buffer to 0x00 */
PLT_Memory_Array[TX_Message_Length] =
0x00
;
/* Enable Interrupt reporting for all events */
PLT_Memory_Array[INT_Enable] = (INT_UnableToTX | INT_TX_NO_ACK |
INT_TX_NO_RESP | INT_RX_Packet_Dropped | INT_RX_Data_Available |
INT_TX_Data_Sent);
5. Place a Timer8 user module with the parameters as shown below. This Timer is used to provide
the timing for several operations such as switch debounce and time interval between changes in
LCD display.
28 Logical Address of Node
Local_LA_LSB
Local_LA_MSB
0
In this project, Logical Address
is set in the code.
29
Single Group Membership
ID
Local_Group
0
For this example project Group
Membership is not used
30
Multiple Group
Membership ID
Local_Group_Hot
0x0
For this example project Group
Membership is not used
31 FSK Bandwidth
Modem_ Config
3 kHz (default)
Separation of FSK signals for
logic ‘1’ and ‘0’
32 Modem Tx Delay
Modem_ Config
7 ms (default)
This value is dependent on the
BAUD rate
Table 5-2. Parameters
Name
TickTimer
Clock
VC3
Capture
Low
TerminalCountOut
None
CompareOut
None
Period
192
CompareValue
100
CompareType
Less Than or Equal
Table 5-1. PLT UM Configuration
(continued)
No.
Property
Register
Value
Details
Содержание CY3274
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