CY3274 Cypress High Voltage Programmable PLC Development Kit Guide, Doc. # 001-53598 Rev. *G
67
Code Examples
5.3.3
I
2
C Interface Write Packet Structure
The I
2
C interface follows the packet structure defined by the I
2
C specification. The write packet is as
follows. The master always sends the entire packet.
5.3.4
I
2
C Interface Read Packet Structure
The I
2
C interface follows the packet structure defined by the I
2
C specification. The read packet is as
follows. The master sends the first byte. The offset is set by sending a write packet for that offset
(sending data is not necessary).
5.3.5
I
2
C Application
The I
2
C write and read messages are processed automatically by the EzI2Cs user module by the
ISRs associated with the user module. It is important to note that I
2
C interrupts are disabled by the
PLT user module when it is transmitting. During this time, if the host initiated an I
2
C message, the
CY8CPLC20 device holds the SCL bus low until it finishes transmitting the PLC packet. It then
resumes processing the I
2
C message.
7
6
5
4
3
2
1
0
Byte 0
I2C Address (0b0000001)
0
Byte 1
Offset
Byte 2+
Data from host to CY8CPLC20 (Optional)
7
6
5
4
3
2
1
0
Byte 0
I2C Address (0b0000001)
1
Byte 1+
Data from CY8CPLC20 to host
Содержание CY3274
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