Contec CNT-3204MT-LPE, Руководство пользователя

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3. External Connection
36
CNT-3204MT-LPE
External sampling clock signal (EXTCLK)
Pin used to input the external pacer clock. The maximum frequency is 10MHz.
If the external clock input is selected as the sampling clock, sampling occurs on the falling edge of the
signal.
Figure 3.12. External sampling clock signal
Other control input signals (DI0 - DI3, EXTSTART, EXTSTOP)
These signals are TTL level compatible and the trigger edge is software-programmable at either the
rising or falling edge. High- and low-level hold times of at least 50 nsec are required to detect an edge
of the signal.
Figure 3.13. Control input signals
EXTCLK
t
PWH
t
PWH : High-level clock pulse width 50nsec (Min.)
t
PWL : Low-level clock pulse width 50nsec (Min.)
t
PWL
t
HIH
t
HIH : High-level hold time 50nsec (Min.)
t
HIL : Low-level hold time 50nsec (Min.)
t
HIL
t
HIH