Copyright
©
2011
congatec
AG
BM67_BS67m02
62/101
Signal
Pin # Description
I/O
PU/PD
Comment
PEG_TX0-
PEG_TX1-
PEG_TX2-
PEG_TX3-
PEG_TX4-
PEG_TX5-
PEG_TX6-
PEG_TX7-
PEG_TX8-
PEG_TX9-
P
PEG_TX10-
P
PEG_TX11-
P
PEG_TX12-
P
PEG_TX13-
P
PEG_TX14-
P
PEG_TX15-
D52
D53
D55
D56
D58
D59
D61
D62
D65
D66
D68
D69
D71
D72
D74
D75
D78
D79
D81
D82
D85
D86
D88
D89
D91
D92
D94
D95
D98
D99
D101
D102
PCI Express Graphics Transmit Output differential pairs. Some of these lines are multiplexed
with SDVO lines.
Note: Can also be used as PCI Express Transmit Output differential pairs 16 through 31
known as PCIE_TX[16-31] + and -.
O PCIE
Not supported
PEG_LANE_RV#
D54
PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane
order.
I 1.05V
Not supported
PEG_ENABLE#
D97
Strap to enable PCI Express x16 external graphics interface.
I 3.3V
PU 10k 3.3V Not supported
Note
The PCI Express Graphics (PEG) signals are multiplexed with HDMI, DisplayPort (DP) and SDVO. The signals for these interfaces are routed
to the PEG interface of the COM Express connector. Refer to the SDVO, HDMI and DiplayPort signal description tables in this section for
information about the signals routed to the PEG interface of the COM Express connector.