
Copyright
©
2011
congatec
AG
BM67_BS67m02
53/101
Table 12 SPI BIOS Flash Interface Signal Descriptions
Signal
Pin #
Description
I/O
PU/PD
Comment
SPI_CS#
B97
Chip select for Carrier Board SPI BIOS Flash.
O 3.3VSB
Carrier shall pull to SPI_POWER when
external SPI provided but not used.
SPI_MISO
A92
Data in to module from carrier board SPI BIOS flash.
I 3.3VSB
SPI_MOSI
A95
Data out from module to carrier board SPI BIOS flash.
O 3.3VSB
SPI_CLK
A94
Clock from module to carrier board SPI BIOS flash.
O 3.3VSB
SPI_POWER A91
Power source for carrier board SPI BIOS flash. SPI_POWER shall be used to power
SPI BIOS flash on the carrier only.
+ 3.3VSB
BIOS_DIS0#
A34
Selection strap to determine the BIOS boot device.
I 3.3VSB
PU 10K
3.3VSB
Carrier shall pull to GND or leave no-
connect.
BIOS_DIS1# B88
Selection strap to determine the BIOS boot device.
I 3.3VSB
PU 10K
3.3VSB
Carrier shall pull to GND or leave no-
connect
Table 13 Miscellaneous Signal Descriptions
Signal
Pin #
Description
I/O
PU/PD
Comment
I2C_CK
B33
General purpose I²C port clock output/input
I/O 3.3V
PU 4K7 3.3VSB
I2C_DAT
B34
General purpose I²C port data I/O line
I/O 3.3V
PU 4K7 3.3VSB
SPKR
B32
Output for audio enunciator, the “speaker” in PC-AT systems
O 3.3V
SPEAKER is a boot strap signal
(see note below)
WDT
B27
Output indicating that a watchdog time-out event has occurred.
O 3.3V
KBD_RST#
A86
Input to module from (optional) external keyboard controller that can force a reset.
Pulled high on the module. This is a legacy artifact of the PC-AT.
I
PU 10K 3.3V
KBD_A20GATE
A87
Input to module from (optional) external keyboard controller that can be used to
control the CPU A20 gate line. The A20GATE restricts the memory access to the
bottom megabyte and is a legacy artifact of the PC-AT. Pulled high on the module.
I
PU 10K 3.3V
Note
Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 7.5 of this user’s guide.