1.2
The PP 110/01x - Main Features
The PP 110/01x is a member of the Concurrent Technologies range of single-board computers
for the CompactPCI bus architecture. It has been designed as a powerful single board computer
based upon the Pentium III-M processor, the 82546EB dual channel Gigabit Ethernet controller,
and the 69030 Graphics Controller. It also provides two IEEE 1386.1 PMC interfaces, optional
on-board mass storage, and interfaces for standard PC-AT based peripherals.
1.2.1
Central Processor
The central processor used on this board is an ultra high performance low power Intel
®
Pentium
III-M 32-bit microprocessor, operating internally at 800MHz or 1.2GHz. The processor supports
the Dual Independent Bus (DIB) architecture with the backside bus connected to the on die
Level 2 cache and the frontside bus connected to the memory controller at 133MHz. The
processor is capable of addressing 4 Gbytes of physical memory all of which is cacheable, and
64 Terabytes of virtual memory. The Pentium III-M is upwardly code-compatible with the other
members of the x86 family of microprocessors.
The processor has an in-built floating point coprocessor for compatibility with 486 and 386/387
designs.
The processor features Data Prefetch Logic that speculatively fetches data to the Level 2 cache
before a Level 1 cache request occurs. This reduces latency resulting in improved performance.
1.2.2
Cache Memories
The Level 1 and Level 2 caches are both implemented on the processor die for maximum
performance. The Level 1 cache is 32 Kbytes in size and the Level 2 cache is 512 Kbytes.
The Level 1 cache is organized as 4-way set associative with a 32-byte line size. It is split into a
16 Kbyte instruction cache and a 16 Kbyte write-back data cache.
The Level 2 cache is organized as 8-way set associative with a 32-byte line size. It operates at
the core frequency and is based on Intel’s Advanced Transfer Cache architecture. The Level 2
cache data is ECC protected.
1.2.3
Chipset
The PP 110/01x uses the ServerWorks ServerSet™ III LE chipset. This is comprised of the
CNB30LE North Bridge and the CSB5 South Bridge.
The CNB30LE interfaces to the CPU host bus. It provides an SDRAM memory controller and two
PCI bus bridges. It supports concurrent CPU and PCI bus operations. Pentium III burst and
pipelining modes are supported to achieve a transfer rate of up to 425 Mbytes/s from SDRAM.
The CSB5 South Bridge provides a variety of peripheral functions including EIDE controllers,
USB controller, LPC (Low Pin Count) Bus bridge, interrupt controller and other legacy PC-AT
architectural functions. It is connected to the CNB30LE primary PCI bus.
The LPC Bus is used to connect to the on-board PC87417 Super I/O Controller and the
PC87391 Super I/O controller on the AD PP5/001 Transition Module. These devices implement
the floppy disk controller, serial ports, parallel port, keyboard and mouse controller and the
real-time clock.
1.2.4
SDRAM
The on-board SDRAM operates at 133MHz and features ECC data protection. The board
contains up to 1 Gbyte of soldered-on SDRAM. A 144-pin SODIMM socket is provided for
memory expansion. This accepts a standard PC133 SDRAM module having a capacity up to
512 Mbytes. Hence a maximum of 1.5 Gbytes of SDRAM may be fitted to the board.
1-2
PP 110/01x
Introduction and Overview
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