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CMS80F731x Reference Manual
10.4.6
Capture Mode
Each of the four 16-bit registers {RLDH,RLDL}, {CCH1,CCL1}, {CCH2,CCL2}, {CCH3,CCL3} can be used to latch the
current 16-bit value of {TH2,TL2}. This feature provides two different capture modes.
In mode 0, an external event can latch the contents of timer 2 into the capture register.
In mode 1, the capture operation occurs when a low-bit byte (RLDL/CCL1/CCL2/CCL3) is written to the 16-bit capture
register. This mode allows the software to read the contents of {TH2,TL2} at runtime.
Capture channels 0 to 3 select the capture input pins CAP0 to CAP3 as the input source signal.
10.4.6.1
Capture Mode 0
In capture mode 0, positive, negative, or positive and negative transactions on capture channels 0 to 3 (CAP0 to CAP3)
will produce capture events. When a capture event occurs, the timer's count value lock is stored in the corresponding capture
register.
Whether a positive transaction triggers capture operation or a negative transaction triggers capture operation on capture
channel 0 depends on the I3FR bit of T2CON. I3FR=0, negative transaction trigger capture; I3FR=1, positive transaction
trigger capture.
Whether a positive transaction trigger capture operation or a negative transaction trigger capture operation on capture
channels 1 to 3 depends on the CAPES bit of the T2CON. CAPES=0, positive transaction trigger capture; CAPES= 1,
negative transaction trigger capture. The transition mode for the selection of capture channels 1 to 3 is the same
Capture channels 0 to 3 support double- transactions capture operations at the same time. Select the corresponding
operating mode control bit of the CCEN register to 11, and the channel supports double- transaction capture operation. It
should be noted that this mode of operation also supports capture mode 1, that is, the write operation can produce a capture
action.
In capture mode 0, external capture events from capture channel 0 to 3 can produce interrupt.
The block diagram of Capture Mode 0 is shown in the following figure:
TL2
TH2
RLDL/CCLx
(x=1,2,3)
RLDH/CCHx
(x=1,2,3)
Capture
CLK
CAPx(x=0,1,2,3)
T2CON[6:5]
CCEN[7:0]
T2CxIF(x=0,1,2,3)
