Cmsemicon CMS80F731 Series, Справочное руководство

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Rev.
1.00
CMS80F731x Reference Manual
4.2.5
Function Clock Control Registers
Watchdog overflow time/timer clock source selection register CKCON
0x8E Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CKCON WTS2 WTS1 WTS0 T1M T0M -- -- --
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 1 1 1
Bit7~Bit5 WTS<2:0>: WDT overflow time selection bits;
000=
2
17
*Tsys;
001=
2
18
*Tsys;
010=
2
19
*Tsys;
011=
2
20
*Tsys;
100=
2
21
*Tsys
101=
2
22
*Tsys;
110= 2
24
*Tsys;
111=
2
26
*Tsys.
Bit4 T1M: Timer1's clock source select bit;
0= Fsys/12;
1= Fsys/4.
Bit3 T0M: Clock source select bit of Timer0;
0= Fsys/12;
1= Fsys/4.
Bit2~Bit0 -- Reserved, must be 1.
UART0/1 baud rate selection register FUNCCR
0x91 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FUNCCR
-- UART1_CKS2 UART1_CKS1 UART1_CKS0 -- UART0_CKS2 UART0_CKS1 UART0_CKS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7 --
Reserved, must be 0.
Bit6~Bit4 UART1_CKS<2:0>: Timer clock source selection for UART1;
000= Overflow clock for Timer1;
001= Overflow clock for Timer4;
010= Overflow clock for Timer2;
011= BRT overflow clock;
Other = Forbidden Access.
Bit3 --
Reserved, must be 0.
Bit2~Bit0 UART0_CKS<2:0>: Timer clock source selection for UART0;
000= Overflow clock for Timer1;
001= Overflow clock for Timer4;
010= Overflow clock for Timer2;
011= BRT overflow clock;
Other = Forbidden Access.