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CMS80F731x Reference Manual
6.4.5
Special Interrupt Flag Bits in Debug Mode
The flag bit in the system is not written to zero to the flag bit, but requires reading/writing other registers to clear the flag
bit.
In debug mode, after breakpoint execution, step-through, or stop operation, the emulator reads out all register values from
the system to the emulation software, and the emulator reads/writes exactly the same as in normal mode.
So during debugging, after a pause occurs, the break flag bit of a set of 1 should appear, but it is displayed as 0 in the
observation window.
Example: The transmit completion flag bit SPISIF in the SPI interrupt flag register in debug mode
...// Set the port and interrupt enable
SPDR = 0x56; Send SPDR data
delay();
...
void SPI_int (void) interrupt SPI_VECTOR// SPI interrupt service program
{
O
1
_nop_(); Set breakpoint 1
_nop_();
O
2
k = SPSR; Set breakpoint 2
_nop_();
...
}
When the breakpoint is running, stop after breakpoint 1, SPI completes the transmit operation, and the transmit
completion interrupt has been generated, so SPSR.7=1, at which point the emulator has completed the operation of reading
all the registers at once (including reading SPSR),
Perform the breakpoint run again, stop after breakpoint 2, at which point the emulator again finishes reading all registers
(including SPDR), so SPSR.7=0. The above situation can also occur when you step into it twice, which requires attention in
debug mode.
