CHAINTECH CT-9PJL, Руководство пользователя

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Appendix
40 Test 8259 interrupt mask bits for channel 2.
43
Test 8259 functionality.
47 Initialize EISA slot
49
1. Calculate total memory by testing the last double word of each
64K page.
2. Program writes allocation for AMD K5 CPU.
4E
1. Program MTRR of M1 CPU
2. Initialize L2 cache for P6 class CPU & program CPU with
proper cacheable range.
3. Initialize the APIC for P6 class CPU.
4. On MP platform, adjust the cacheable range to smaller one in
case the cacheable ranges between each CPU are not identical.
50 Initialize USB
52 Test all memory (clear all extended memory to 0)
55 Display number of processors (multi-processor platform)
57
1. Display PnP logo.
2. Early ISA PnP initialization
- Assign CSN to every ISA PnP device.
59
Initialize the combined Trend Anti-Virus code.
5B
(Optional Feature) Show message for entering AwdFlash.EXE from
FDD (optional)
5D
1. Initialize Init_Onboard_Super_IO switch.
2. Initialize Init_Onbaord_AUDIO switch.
60
Okay to enter Setup utility; i.e. not until this POST stage can users
enter the CMOS setup utility.
65
Initialize PS/2 Mouse
67 Prepare memory size information for function call: INT 15h ax=E820h
69 Turn on L2 cache
6B
Program chipset registers according to items described in Setup &
Auto-configuration table.
6D
1. Assign resources to all ISA PnP devices.
2. Auto assign ports to onboard COM ports if the corresponding
item in Setup is set to “AUTO”.
6F 1. Initialize floppy controller.
71