CAENels DAMC-FMC2ZUP, Руководство пользователя

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DAMC-FMC2ZUP User’s Manual DAMC-FMC2ZUP Architecture
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2.1.3 FMC HPC (VITA 57.1)
The following interconnections are available over the FMC connector:
•
LA (00-33) LVDS Differential pairs:
All the LA signals of the FMC interface are routed to the PL section of the FPGA.
Two FPGA banks are associated to this interface, LA-00 to LA-16 are connected to
one bank while LA-17 to LA-33 are routed to the other. LA-00 and LA-17 are clock
capable pins routed to dedicated inputs on the FPGA, this gives them access to the
clock resources on the PL.
•
HA (00-23) LVDS Differential pairs :
All the HA signals of the FMC interface are routed to the PL section of the FPGA. All
the signals reside on the same I/O bank, HA-00, HA-01 and HA-17 are clock capable
pins and are routed to dedicated inputs on the FPGA, giving them access to the clock
resources of the PL.
•
MGT interfaces:
A total of 8 GTH MGTs (two full MGT Quads) are available on the FMC connector.
•
CLK0-M2C and CLK1-M2C :
Both signals are available and connected on dedicated clock input resources on the PL
section of the FPGA. CLK0 resides in the same I/O bank as LA-00 to LA-16 and
CLK1 resides in the same I/O bank as LA-17 to LA-33.
•
GBT-CLK0 and GBT-CLK1:
Both signals are available and connected to the dedicated reference clock input
resources on the PL MGT Quads. CLK0 resides in the same Quad as MGT lanes 0 to
3 and CLK1 resides in the same Quad as MGT lanes 4 to 7.