DAMC-FMC2ZUP User’s Manual
DAMC-FMC2ZUP Architecture
21
2.4
JTAG Chain
The board implements two, not fully independent, JTAG chains. The main JTAG
chain can be accessed through the P1 Connector (see Figure 1-1 for location on board)
or the MicroTCA backplane and is "mediated" by the MMC Stamp SoM. The MMC
Stamp is responsible to select and/or insert more devices into the JTAG chain. The
connected devices are:
•
Main FPGA PS JTAG Interface with all internal Controllers accessible by
default (refer to Xilinx UG1085
Figure 39-1)
•
Secondary FPGA JTAG Interface
•
FMC and FMC+ connectors JTAG signals
•
RTM JTAG chain
Figure 2-4:
Main JTAG chain
The second JTAG chain is accessible from Connector P4 (see Figure 1-1 for
location on board) and includes only the Main FPGA Arm DAP Controller to
facilitate the software development on the PS of the Zynq ARM CPUs (refer to Xilinx
UG1085
Chapter 39, PJTAG/Arm DAP Sections) by
providing a dedicated debug interface.
Figure 2-5:
ARM JTAG
Содержание DAMC-FMC2ZUP
Страница 14: ...DAMC FMC2ZUP User s Manual DAMC FMC2ZUP Architecture 14 Figure 2 1 Block Diagram...
Страница 19: ...DAMC FMC2ZUP User s Manual DAMC FMC2ZUP Architecture 19 Figure 2 2 Clock Network Diagram...
Страница 33: ...DAMC FMC2ZUP User s Manual Appendix 33 Figure 5 6 FMC connections...
Страница 34: ...DAMC FMC2ZUP User s Manual Appendix 34 Figure 5 7 FMC connections...
