CAENels DAMC-FMC2ZUP, Руководство пользователя

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DAMC-FMC2ZUP User’s Manual DAMC-FMC2ZUP Architecture
15
2.1.2 FMC+ (VITA 57.4)
The following interconnections are available over the FMC+ connector:
•
LA (00-33) LVDS Differential pairs:
All the LA signals of the FMC interface are routed to the PL section of the FPGA.
Two FPGA banks are associated to this interface, LA-00 to LA-16 are connected to
one bank while LA-17 to LA-33 are routed to the other. LA-00, LA-01, LA-17 and
LA-18 are clock capable pins routed to dedicated inputs on the FPGA, these signals
have access to the clock resources on the PL.
•
HA (00-23) LVDS Differential pairs:
All the HA signals of the FMC interface are routed to the PL section of the FPGA. All
the signals reside on the same I/O bank, HA-00, HA-01 and HA-17 are clock capable
pins and are routed to dedicated inputs on the FPGA allowing them to access the
clock resources of the PL.
•
MGT interfaces:
A total of 24 MGT (6 full MGT Quads) are provided to the FMC connector. 16 GTY
Transceivers up to 28.21 Gb/s and 8 GTH Transceivers up to 16.375 Gb/s or 12.5
Gb/s (low power mode).
•
CLK0-M2C and CLK1-M2C:
Both signals are available and connected on dedicated clock input resources on the PL
section of the FPGA. CLK0 resides in the same I/O bank as LA-00 to LA-16 and
CLK1 resides in the same I/O bank as LA-17 to LA-33.
•
GBT-CLK0, GBT-CLK1 and GBT-CLKHS 2 to 5:
All signals are available and connected to the dedicated reference clock input
resources of the associated PL MGT Quads. CLK0 resides in the same Quad as MGT
lanes 0 to 3 and CLK1 resides in the same Quad as MGT lanes 4 to 7, CLKHS2
resides in the same Quad as MGT lanes 8 to 11 and so on.